Apparatus, system, and method for solid-state storage as cache for high-capacity, non-volatile storage

• US 9,519,594 B2
• Filed: 10/09/2012
• Issued: 12/13/2016
• Est. Priority Date: 12/06/2006
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Flynn, David, Strasser, John, Thatcher, Jonathan, Zappe, Michael
• Primary Examiner(s): Alsip, Michael
• Application Number:
  US13/648,009
• Publication Number:
  US 20130097367A1
• Time in Patent Office: 1,526 Days
• Field of Search: 711/113, 711/E12.019
• US Class Current: 1/1
• CPC Class Codes: G06F 1/183 Internal mounting support structures, e.g. for printed circuit boards, internal connecting means for buses G06F13/409
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/426 using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
• CPC Class Codes: G06F 2211/002 Bus
• CPC Class Codes: G06F 2211/103 Hybrid, i.e. RAID systems with parity comprising a mix of RAID types
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/70 Details relating to dynamic memory management
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7208 : Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0604 : Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0608 : Saving storage space on storage systems
• CPC Class Codes: G06F 3/0613 : in relation to throughput
• CPC Class Codes: G06F 3/0619 : in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0643 : Management of files
• CPC Class Codes: G06F 3/065 : Replication mechanisms
• CPC Class Codes: G06F 3/0652 : Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0656 : Data buffering arrangements
• CPC Class Codes: G06F 3/0659 : Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 : Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0685 : Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 9/52 : Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/54 : Interprogram communication
• CPC Class Codes: H04L 67/02 : based on web technology, e.g. hypertext transfer protocol [HTTP]
• CPC Class Codes: H04L 67/1097 : for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H05K 7/1444 : Complex or three-dimensional-arrangements; Stepped or dual mother boards
• CPC Class Codes: H05K 7/1487 : Blade assemblies, e.g. blade cases or inner arrangements within a blade
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus, system, and method are disclosed for solid-state storage as cache for high-capacity, non-volatile storage. The apparatus, system, and method are provided with a plurality of modules including a cache front-end module and a cache back-end module. The cache front-end module manages data transfers associated with a storage request. The data transfers between a requesting device and solid-state storage function as cache for one or more HCNV storage devices, and the data transfers may include one or more of data, metadata, and metadata indexes. The solid-state storage may include an array of non-volatile, solid-state data storage elements. The cache back-end module manages data transfers between the solid-state storage and the one or more HCNV storage devices.

Claims

1. A method, comprising:

maintaining entries in a logical-to-physical mapping index of a storage controller in response to storing data on the solid-state storage medium, wherein the storage controller maintains the entries to associate logical identifiers corresponding to the stored data with respective storage addresses of the stored data on the solid-state storage medium;

admitting data of a back-end storage system into a cache on the solid-state storage medium by,

caching data of the back-end storage system at respective storage addresses of the solid-state storage medium, and

associating logical identifiers of the back-end storage system corresponding to the cached data with respective storage addresses of the cached data on the solid-state storage medium by use of the logical-to-physical mapping index of the storage controller;

servicing a request to access data corresponding to a specified logical identifier of the back-end storage system by,

determining whether data of the specified logical identifier is cached on the solid-state storage medium based on whether a particular entry for the specified logical identifier exists in the logical-to-physical mapping index of the storage controller, and

in response to determining that data of the specified logical identifier is cached on the solid-state storage medium, reading cached data of the specified logical identifier from the solid-state storage medium at a first storage address associated with the particular entry; and

updating the particular entry in the logical-to-physical mapping index of the storage controller to associate the specified logical identifier with a second storage address on the solid-state storage medium in response to the storage controller relocating the cached data of the specified logical identifier to the second storage address on the solid-state storage medium, wherein the particular entry is updated while retaining the particular entry in the logical-to-physical mapping index such that the cached data corresponding to the specified logical identifier is retained in the cache during the relocating.

2. The method of claim 1, further comprising caching the data of the back-end storage system on the solid-state storage medium in a format that associates the cached data with respective logical identifiers of the back-end storage system.

3. The method of claim 1, further comprising associating sequence indicators with the cached data of the back-end storage system on the solid-state storage medium, wherein the sequence indicators determine an ordered sequence of storage operations performed on the solid-state storage medium by the storage controller.

4. The method of claim 3, further comprising:

caching the data of the back-end storage system on the solid-state storage medium in a format that associates the cached data with respective logical identifiers of the back-end storage system; and

reconstructing entries of the logical-to-physical mapping index using the logical identifiers and the sequence indicators associated with the data of the back-end storage system cached on the solid-state storage medium.

5. The method of claim 4, wherein the logical identifiers of the back-end storage system corresponding to the data of the back-end storage system cached on the solid-state storage device correspond to addresses of the back-end storage system.

6. The method of claim 5, wherein reconstructing entries of the logical-to-physical mapping index comprises replaying a sequence of changes made to the entries of the logical-to-physical mapping index using the respective logical identifiers and the sequence indicators associated with the data of the back-end storage system cached on the solid-state storage medium.

7. The method of claim 4, further comprising marking storage divisions of the solid-state storage medium with respective sequence indicators.

8. The method of claim 1, wherein caching the data of the back-end storage system on the solid-state storage medium further comprises:

caching the data of the back-end storage system in error-correcting code (ECC) blocks, wherein the ECC blocks comprise respective portions of the data of the back-end storage system and a corresponding error-correcting code configured to correct errors in the ECC block;

storing a first portion of one of the ECC blocks on a first storage element of the solid-state storage device; and

storing a second portion of the ECC block on a second storage element of the solid-state storage device.

9. The method of claim 1, wherein caching the data of the back-end storage system on the solid-state storage medium further comprises:

packetizing the data of the back-end storage system into one or more packets, each packet having a header comprising a logical identifier of the back-end storage system corresponding to the data; and

storing the one or more packets sequentially on the solid-state storage medium.

10. The method of claim 9, further comprising:

storing a first portion of one of the packets on a first storage element of the solid-state storage medium; and

storing a second portion of the packet on a second storage element of the solid-state storage medium.

11. The method of claim 9, further comprising:

storing a first portion of one of the packets on a first storage element of the solid-state storage medium and a second portion of the packet on a second storage element of the solid-state storage medium in response to a single write command.

12. The method of claim 1, wherein a write execution time of the solid-state storage medium is greater than a read execution time of the solid-state storage medium, and wherein caching the data of the back-end storage system comprises:

buffering the data of the back-end storage system on a write data buffer; and

storing the buffered data on a logical page, the logical page comprising physical pages on each of a plurality of solid-state storage elements.

13. The method of claim 12, wherein the solid-state storage elements of the logical page are arranged in parallel, and wherein the buffered data is stored on the plurality of solid-state storage elements comprising the logical page in response to a single write command.

14. The method of claim 12, wherein the solid-state storage medium is a write-once storage medium, and wherein an erase execution time of the solid-state storage medium is greater than a write execution time of the solid-state storage medium, the method further comprising erasing a logical storage division comprising a plurality of logical pages of the solid- state storage elements in parallel.

15. The method of claim 1, further comprising:

partitioning the solid-state storage medium into a first portion and a second portion;

caching the data of the back-end storage system in the first portion of the solid-state storage medium; and

storing non-cache data in the second portion of the solid-state medium.

16. The method of claim 15, wherein the data of the back-end storage system is cached on a storage division of a solid-state storage medium with non-cache data.

17. The method of claim 1, further comprising storing cache control metadata pertaining to the data of the back-end storage system cached on the solid-state storage medium sequentially with the non-cache data on the solid-state storage device.

21. The method of claim 1, further comprising relocating the cached data of the specified logical identifier to the second storage address on the solid-state storage medium in response to one or more of a request to write data to the specified logical identifier of the back-end storage system, a request to modify the cached data corresponding to the specified logical identifier of the back-end storage system, a request to overwrite the cached data corresponding to the specified logical identifier of the back-end storage system, a grooming operation on the solid-state storage medium, garbage collection on the solid-state storage medium, and a recovery operation on the solid-state storage medium.

18. A non-transitory computer-readable storage medium comprising instructions to cause a computing device to perform a method, the method comprising:

caching data of a primary storage system on a cache comprising a solid-state storage medium in response to storage requests directed to the primary storage system, wherein the cached data corresponds to respective identifiers of the primary storage system, and wherein caching the data of the primary storage system comprises,

storing the data of the primary storage system at respective physical addresses of the solid-state storage medium, and

maintaining entries in a logical-to-physical translation index, the entries associating identifiers corresponding to cached data of the primary storage system with respective physical addresses at which the cached data is stored on the solid-state storage medium;

servicing a read request pertaining to a specified identifier of the primary storage system, wherein servicing the read request comprises,

identifying an entry of the logical-to-physical translation index for the specified identifier of the primary storage system,

using the identified entry to determine a physical address at which cached data of the specified identifier is stored on the solid-state storage medium, and

retrieving the cached data of the specified identifier from the solid-state storage medium at the determined physical address; and

modifying the particular entry of the logical-to-physical translation index to associate the specified identifier with a different physical address of the solid-state storage medium in response to moving the cached data of the specified identifier to the different physical address on the solid-state storage medium, wherein the particular entry is modified while retaining the particular entry in the logical-to-physical translation index, and while retaining the cached data of the specified logical identifier in the cache.

19. The non-transitory computer-readable storage medium of claim 18, wherein physical addresses of the solid-state storage medium are associated with respective storage divisions, the method further comprising marking storage divisions of the solid-state storage medium comprising the cached data of the primary storage system with respective sequence numbers to determine a temporal order of the storage divisions.

20. An apparatus comprising:

a storage controller configured to write data to respective storage locations of a solid-state storage device;

an index module configured to maintain a logical-to-physical translation index comprising entries that associate logical addresses of data stored on the solid-state storage device with respective storage locations of the solid-state storage device;

a cache module configured to cache data of a high-capacity storage system in a cache on the solid-state storage device by use of the storage controller, wherein to cache data associated with a specified logical address of the high-capacity storage system, the storage controller writes the data to a first storage location on the solid-state storage device and the index module associates the specified logical address of the high-capacity storage system with the first storage location in a designated entry of the logical-to-physical mapping index;

wherein the cache module is further configured to service an access request pertaining to the specified logical address of the high-capacity storage system, wherein to service the data request the cache module determines that the specified logical address is stored in the cache on the solid-state storage device based on identifying the designated entry in the logical-to-physical mapping index, and the storage controller reads the first storage location of the solid-state storage device associated with the specified logical address by the designated entry,

wherein the index module is configured to alter the designated entry of the logical-to-physical mapping index in response to the storage controller relocating the data stored on the first storage location to a second storage location on the solid-state storage device, wherein the index module alters the designated entry to associate the specified logical address of the high-capacity storage system with the second storage location on the solid-state storage device while maintaining the designated entry in the logical-to-physical translation index such that the data of the specified logical address is retained in the cache on the solid-state storage device while the designated entry is altered.

22. The apparatus of claim 20, wherein the index module is configured to alter the designated entry in response to one or more of writing data corresponding to the specified logical address to the second storage location, modifying the data corresponding to the specified logical address, a grooming operation on the solid-state storage device, a recovery operation on the solid-state storage device, and garbage collection on a storage division comprising the first storage location.