Method, apparatus, and system for operating shared resource in asynchronous multiprocessing system

• US 9,519,652 B2
• Filed: 04/25/2013
• Issued: 12/13/2016
• Est. Priority Date: 04/27/2012
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Su, Qing, Liu, Yu, Guo, Xiancheng, Liu, Hu
• Primary Examiner(s): Le, Miranda
• Application Number:
  US13/870,586
• Publication Number:
  US 20130290286A1
• Time in Patent Office: 1,328 Days
• Field of Search: 707/704, 707/687
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 16/1774 Locking methods, e.g. locking methods for file systems allowing shared and concurrent access to files

Abstract

Technical effects of a method, an apparatus, and a system for operating a shared resource in an asynchronous multiprocessing system that are provided in the present invention are as follows: A processor in an asynchronous multiprocessing system implements an operation on a shared resource by locking a hardware resource lock, and the hardware resource lock is implemented by a register; in this way, a bus in the asynchronous multiprocessing system does not need to support a synchronization operation, and the processor also does not need to have a feature of supporting a synchronization operation, and is capable of implementing the operation on the shared resource only in a manner of accessing the register, which simplifies the operation on the shared resource by the processor in the asynchronous multiprocessing system, enlarges a selection range of the processor in the asynchronous multiprocessing system, and further improves flexibility of the asynchronous multiprocessing system.

Claims

1. A method for operating a shared hardware resource in an asynchronous multiprocessing system, comprising:

accessing by a first and a second processor in the asynchronous multiprocessing system, a shared hardware resource through a same hardware resource lock register, wherein the same hardware resource lock register is coupled to the first and the second processor which are separately located from the same hardware resource lock register through first and second respective buses;

wherein the same hardware resource lock register is implemented by a plurality of register circuitry portions comprised within the same hardware resource lock register, including;

a first register circuitry portion comprising a lock register circuitry portion,

a second register circuitry portion comprising an unlock circuitry register portion, and

a third register circuitry portion comprising a lock state register circuitry portion;

the method comprising;

receiving by a first input of the lock register circuitry portion, a lock command sent from the first processor in the asynchronous multiprocessing system, wherein the lock command is multiplexed with a lock state signal received at a second input of the lock register circuitry portion, wherein the received lock state signal is sent from the lock state register circuitry portion of the same hardware resource lock register to further perform one of the following;

when the received lock state signal at the second input of the lock register circuitry portion is in an unlock state, outputting by the lock register circuitry portion, a lock enable signal to the lock state register circuitry portion to set the same hardware resource lock register to a state of being locked by the first processor, so that the first processor operates the shared resource, wherein after the setting, by the lock state register circuitry portion, the state of the same hardware resource lock register to a state of being locked by the first processor in order that the first processor operates the shared resource, the method further comprises;

receiving at a first input of the unlock register portion;

an unlock command sent by the first processor to trigger an output by the unlock register portion, and a resource unlock enable command to a first input of the lock state register portion; and

restoring, by the lock state register portion of the hardware resource lock, the state of the same hardware resource lock register to the unlocked state according to the received unlock command;

or

ignoring by the lock register circuitry portion, the lock command at the first input when the received lock state signal at the second input of the lock register circuitry portion is in a lock state.

2. The method according to claim 1, wherein before receiving by the lock register circuitry portion of the same hardware resource lock register the first input of the lock command sent by the first processor in the asynchronous multiprocessing system, the method further comprises:

receiving at the first input of the lock register circuitry portion, a first query command sent by the first processor, wherein the first query command is used to query a state of the hardware resource lock; and

returning by the lock state register circuitry portion, the state of the hardware resource lock register to the first processor.

3. The method according to claim 1, wherein after the ignoring by the lock register circuitry portion of the lock command at the first input, or setting by the lock state register circuitry portion, the hardware resource lock register to a state of being locked by the first processor in order that the first processor operates the shared resource, the method further comprises:

receiving at the first input of the lock register circuitry portion, a second query command sent by the first processor, wherein the second query command is used to query whether the hardware resource lock is locked by the first processor; and

returning by the lock state register circuitry portion, a lock result to the first processor.

4. The method according to claim 1, wherein after receiving, at the first input by the lock register circuitry portion of the same hardware resource lock register, a lock command sent by the first processor in the asynchronous multiprocessing system, the method further comprises:

receiving at the first input of the lock register circuitry portion, another lock command sent by the second processor in the asynchronous multiprocessing system; and

ignoring, by the lock register circuitry portion of the hardware resource lock, the another lock command sent by the second processor.

5. The method according to claim 4, wherein before the receiving at the first input of the lock register circuitry portion, the another lock command sent by the second processor in the asynchronous multiprocessing system, the method further comprises:

receiving at the first input of the lock register circuitry portion, a first query command sent by the second processor, wherein the first query command sent by the second processor is used to query a state of the same hardware resource lock register; and

returning by the lock state register circuitry portion, the state of the hardware resource lock to the second processor.

6. The method according to claim 4, wherein after ignoring, by the lock register circuitry portion of the same hardware resource lock register, the another lock command sent by the second processor, the method further comprises:

receiving at the first input of the lock register portion, a second query command sent by the second processor, wherein the second query command sent by the second processor is used to query whether the same hardware resource lock register is locked by the second processor; and

returning by the lock state register circuitry portion, another lock result to the second processor.

7. A method for operating a shared hardware resource in an asynchronous multiprocessing system, comprising:

accessing by a first and a second processor in the asynchronous multiprocessing system, a shared hardware resource through a same hardware resource lock register, wherein the same hardware resource lock register is coupled to the first and the second processor which are separately located from the same hardware resource lock register through first and second respective buses;

wherein the hardware resource lock register is implemented by a plurality of register circuitry portions within the same hardware resource lock register, including;

a first register circuitry portion comprising a lock register circuitry portion,

a second register circuitry portion comprising an unlock circuitry register portion, and

a third register circuitry portion comprising a lock state register circuitry portion, the method comprising;

delivering, by the first processor in the asynchronous multiprocessing system, a lock command to a first input of the lock register circuitry portion of the same hardware resource lock register, and the lock command is multiplexed with a lock state signal received at a second input of the lock register circuitry portion, wherein the received lock state signal is sent from the lock state register circuitry portion of the same hardware resource lock register to further perform one of the following;

when the received lock state signal at the second input of the lock register circuitry portion is in an unlock state, outputting by the lock register circuitry portion, a lock enable signal to the lock state register circuitry portion to set the same hardware resource lock register to a state of being locked by the first processor, so that the first processor operates the shared resource, wherein after the operating, by the first processor, the shared resource, the method further comprises;

sending, by the first processor, an unlock command to a first input of the unlock register circuitry portion of the same hardware resource lock register in order that the lock state register circuitry portion of the same hardware resource lock register restores the state of the same hardware resource lock register to the unlocked state;

or

ignoring by the lock register circuitry portion, the lock command at the first input when the received lock state signal at the second input of the lock register circuitry portion is in a lock state.

8. The method according to claim 7, wherein before the operating, by the first processor, the shared resource, the method further comprises:

reading, by the first processor, a state of the hardware resource lock returned by the lock state register circuitry portion.

9. A hardware resource lock register which is implemented by a plurality of register circuitry portions comprised within the hardware resource lock register, which operate in the shared hardware resource, comprising:

a processor,

a first register circuitry portion comprising a lock register circuitry portion,

a second register circuitry portion comprising an unlock register circuitry portion, and

a third register circuitry portion comprising a lock state register circuitry portion;

wherein;

the lock state register circuitry portion, configured to provide a lock state signal of the same hardware resource lock register; and

the lock register circuitry portion, configured to;

receive at a first input, a lock command sent by the first processor in the asynchronous multiprocessing system, wherein the lock command is multiplexed with a lock state signal received at a second input of the lock register circuitry portion, wherein the received lock state signal is sent from the lock state register circuitry portion of the hardware resource lock to further perform one of the following;

when the received lock state signal at the second input of the lock register circuitry portion is in an unlock state, outputting by the lock register circuitry portion, a lock enable signal to the lock state register circuitry portion to set the same hardware resource lock register to a state of being locked by the first processor, so that the first processor operates the shared resource, wherein after the operating, by the first processor, the shared resource, the method further comprises;

sending, by the first processor, an unlock command to a first input of the unlock register circuitry portion of the same hardware resource lock register in order that the lock state register circuitry portion of the same hardware resource lock register restores the state of the same hardware resource lock register to the unlocked state;

or

not returning any signal by the lock register circuitry portion to the lock state register circuitry portion when the received lock state signal at the second input of the lock register circuitry portion is in a lock state, and ignore the lock command.

10. The hardware resource lock register according to claim 9, wherein the first input of the lock state register circuitry portion is further configured to receive a first query command sent by the first processor, wherein the first query command is used to query a state of the hardware resource lock, and return by the lock state register circuitry portion, the state of the same hardware resource lock register to the first processor.

11. The hardware resource lock register according to claim 9, wherein the first input of the lock state register circuitry portion is further configured to receive a second query command sent by the first processor, wherein the second query command is used to query whether the same hardware resource lock register is locked by the first processor, and return by the lock state register circuitry portion, a lock result to the first processor.

12. The hardware resource lock register according to claim 9, wherein:

the unlock register circuitry portion, configured to set, when the same hardware resource lock register is in an unlocked state, the lock state register circuitry portion of the hardware resource lock to a state of being locked by the first processor, so that after the first processor operates the shared resource, a first input of the unlock register circuitry portion of the same hardware resource lock register receives an unlock command sent by the first processor and restores the lock state register circuitry portion of the same hardware resource lock register to the unlocked state according to the received unlock command.

13. The hardware resource lock register according to claim 9, wherein the lock register circuitry portion is further configured to, after receiving the lock command sent by the first processor in the asynchronous multiprocessing system, receive at the first input of the lock register circuitry portion, another lock command sent by the second processor in the asynchronous multiprocessing system, and ignore the another lock command sent by the second processor.

14. The hardware resource lock register according to claim 13, wherein the lock state register circuitry portion is further configured to, before the lock register circuitry portion receives the another lock command sent by the second processor in the asynchronous multiprocessing system, receive at the first input of the lock register circuitry portion, a first query command sent by the second processor, wherein the first query command sent by the second processor is used to query a state of the same hardware resource lock register, and return by the lock state register circuitry portion, the state of the same hardware resource lock register to the second processor.

15. The hardware resource lock register according to claim 13, wherein the lock state register circuitry portion is further configured to, after the lock register circuitry portion ignores the lock command sent by the second processor, receive at the first input of the lock register portion, a second query command sent by the second processor, wherein the second query command sent by the second processor is used to query whether the same hardware resource lock register is locked by the second processor, and return by the lock state register circuitry portion, a lock result to the second processor.

16. A first processor in an asynchronous multiprocessing system having at least a second processor, comprising:

a lock unit circuitry portion, configured to deliver a lock command to a same hardware resource lock register when the same hardware resource lock register is in an unlocked state, such that the lock unit circuitry portion of the first processor lock the same hardware resource lock register to prevent the second processor from accessing a shared hardware resource through the same hardware resource lock register, wherein the same hardware resource lock register is coupled to the first and the second processor which are separately located from the same hardware resource lock register through first and second respective buses;

wherein the hardware resource lock register is implemented by a plurality of register circuitry portions comprised within the same hardware resource lock register, including;

a first register circuitry portion comprising a lock register circuitry portion,

a second register circuitry portion comprising an unlock register circuitry portion, and

a third register circuitry portion comprising a lock state register circuitry portion;

wherein the lock command is received in a first input of the lock register circuitry portion of the same hardware resource lock register, and the lock command is multiplexed with a lock state signal received at a second input of the lock register circuitry portion, wherein the received lock state signal is sent from the lock state register circuitry portion of the same hardware resource lock register to perform one of the following;

not returning any signal by the lock register circuitry portion to the lock state register circuitry portion when the received lock state signal at the second input of the lock register circuitry portion is in a lock state, or

when the received lock state signal at the second input of the lock register circuitry portion is in an unlock state, outputting by the lock register circuitry portion, a lock enable signal to the lock state register circuitry portion to set the same hardware resource lock register to a state of being locked by the first processor; and

a resource operating unit circuitry portion, configured to operate the shared resource when the same hardware resource lock register is in a state of being locked by the processor, wherein the unlock unit circuitry portion is configured to send an unlock command to a first input of the unlock register portion, wherein the resource operating unit circuitry portion operates the shared resource, so that the lock state register portion of the same hardware resource lock register restores the state of the same hardware resource lock register to the unlocked state.

17. The processor according to claim 16, further comprising:

a lock readback unit circuitry portion, configured to read a state of the same hardware resource lock register before the resource operating unit circuitry portion operates the shared resource.