Enhanced temperature compensation for resistive memory cell circuits

• US 9,520,189 B1
• Filed: 10/29/2015
• Issued: 12/13/2016
• Est. Priority Date: 10/29/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Papandreou, Nikolaos, Pozidis, Charalampos, Stanisavljevic, Milos
• Primary Examiner(s): Auduong, Gene
• Application Number:
  US14/926,569
• Time in Patent Office: 411 Days
• Field of Search: 365/163, 365/148, 365/158, 365/171, 365/189.06, 365/189.15, 365/196, 365/185.03
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0021 Auxiliary circuits
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

In some aspects, a computer-implemented method for performing a voltage-based measurement of a resistive memory cell includes a plurality m of programmable cell states. The method may include providing, via a processor, a prebiased voltage at a connecting node coupled to the resistive memory cell, coupling, via the processor, a resistor circuit in parallel to the resistive memory cell such that the resistor is configured to reduce an effective resistance at the connecting node of the prebiasing circuit, prebiasing a bitline capacitance of the resistive memory cell by the prebiasing circuit, settling, via the processor, a sensing circuit to a target voltage by connecting the sensing circuit to one of a plurality of settling circuits, wherein the one of the plurality of settling circuits is selected based on a temperature reading of the resistive memory cell, sensing a voltage of the resistive memory cell, and outputting a resultant value based on the sensed voltage.

Claims

1. A computer-implemented method for performing a voltage-based measurement of a resistive memory cell having a plurality of programmable cell states, the method comprising:

providing, via a processor, a prebiased voltage at a connecting node coupled to the resistive memory cell;

coupling, via the processor, a resistor circuit in parallel to the resistive memory cell such that the resistor is configured to reduce an effective resistance at the connecting node of the prebiasing circuit;

prebiasing a bitline capacitance of the resistive memory cell by the prebiasing circuit;

settling, via the processor, a sensing circuit to a target voltage by connecting the sensing circuit to one of a plurality of settling circuits, wherein the one of the plurality of settling circuits is selected based on a temperature reading of the resistive memory cell;

sensing a voltage of the resistive memory cell; and

outputting a resultant value based on the sensed voltage.

2. The computer-implemented method of claim 1, wherein settling the sensing circuit comprises reading a temperature sensor to determine the temperature reading.

3. The computer-implemented method of claim 2, wherein the temperature sensor is configured to read a temperature a plurality of memory cells organized as a memory storage bank.

4. The computer-implemented method of claim 2, wherein the temperature sensor is configured to read a temperature at a plurality of memory storage banks.

5. The computer-implemented method of claim 1, wherein the resultant value is constant at all temperatures within a predetermined range of operational temperatures of the resistive memory cell.

6. The computer-implemented method of claim 5, wherein a constant resultant value is within a predefined range of error.

7. The computer-implemented method of claim 1, wherein outputting the sensed voltage is output based on an optimal detection curve.

8. The computer-implemented method of claim 7, wherein the optimal detection curve is determined by:

monitoring the plurality of memory cells at the end of a predetermined time period;

defining a reference temperature nominal detection curve and a mean enhanced voltage-metric value for each of the plurality of m levels;

varying a temperature at each of the plurality of memory cells to a predetermined temperature, wherein the temperature is predetermined with respect to the reference temperature;

reading a current at an output of each of the plurality of memory cells at a mean enhanced voltage-metric value for each of the plurality of m levels; and

calculating the resultant mean value of current for each of the plurality of m levels at the end of the predetermined time period.

9. The computer-implemented method of claim 8, further comprising:

reading the current at the output of each of the plurality of memory cells at a mean enhanced voltage-metric value for each of the plurality of m levels at a plurality of temperatures; and

calculating a plurality of resultant mean values of current for each of the plurality of m levels with respect to each of the plurality of temperatures.

10. A system for performing a voltage-based measurement of a resistive memory cell having a plurality m of programmable cell states, the system comprising:

a processor configured to;

provide a prebiased voltage at a connecting node coupled to the resistive memory cell;

couple a resistor circuit in parallel to the resistive memory cell such that the resistor is configured to reduce an effective resistance at the connecting node of the prebiasing circuit;

prebias a bitline capacitance of the resistive memory cell by the prebiasing circuit;

settle a sensing circuit to a target voltage by connecting the sensing circuit to one of a plurality of settling circuits, wherein the one of the plurality of settling circuits is selected based on a temperature reading of the resistive memory cell;

sense a voltage of the resistive memory cell; and

output a resultant value based on the sensed voltage.

11. The system of claim 10, further comprising a temperature sensor configured to provide the sensed temperature reading.

12. The system of claim 11, wherein the temperature sensor is configured to read a temperature for a plurality of memory cells organized as a memory storage bank.

13. The system of claim 11, wherein the sensor is configured to read a temperature at a plurality of memory storage banks.

14. The system of claim 10, wherein the resultant value is substantially constant at all temperatures within a predetermined range of operational temperatures.

15. The system of claim 14, wherein a substantially constant resultant value is within a predefined range of mean square error.

16. The system of claim 15, wherein the processor is configured to:

monitor the resistive memory cell at the end of a predetermined time period;

vary a temperature at the resistive memory cell to a predetermined temperature, wherein the temperature is predetermined with respect to a reference temperature;

read a current at an output of the resistive memory cell at a mean enhanced voltage-metric value for each of the plurality of m levels;

calculate a resultant mean value of current for each of the plurality of m levels at the end of the predetermined time period; and

determine an optional detection curve based on the calculated value and a mean enhanced voltage-metric value for each of the plurality of m levels.

17. The system of claim 16, wherein the processor is further configured to:

read the current at the output of each of a plurality of memory cells at a mean enhanced voltage-metric value for each of the plurality of m levels at a plurality of temperatures; and

calculate a plurality of resultant mean values of current for each of the plurality of m levels with respect to each of the plurality of temperatures.

18. A computer program product for performing a voltage-based measurement, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions being executable by a processor to cause the processor to perform a method, the method comprising:

providing, via the processor, a prebiased voltage at a connecting node coupled to the resistive memory cell;

coupling, via the processor, a resistor circuit in parallel to the resistive memory cell such that the resistor is configured to reduce an effective resistance at the connecting node of the prebiasing circuit;

prebiasing a bitline capacitance of the resistive memory cell by the prebiasing circuit;

settling, via the processor, a sensing circuit to a target voltage by connecting the sensing circuit to one of a plurality of settling circuits, wherein the one of the plurality of settling circuits is selected based on a temperature reading of the resistive memory cell;

sensing a voltage of the resistive memory cell; and

outputting a resultant value based on the sensed voltage.

19. The computer program product of claim 18, wherein settling the sensing circuit comprises reading a temperature sensor to determine the temperature reading.

20. The computer program product of claim 19, wherein the temperature sensor is configured to read a temperature of a plurality of memory cells organized as a memory storage bank.