Apparatus, systems, and methods for operating flash backed DRAM module

• US 9,520,191 B2
• Filed: 02/17/2015
• Issued: 12/13/2016
• Est. Priority Date: 02/11/2009
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: HGST Technologies Santa Ana, Inc. (Western Digital Corporation)
• Inventors: Moshayedi, Mark, Finke, Douglas
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US14/624,255
• Publication Number:
  US 20150248935A1
• Time in Patent Office: 665 Days
• Field of Search: 711/165, 711/104, 714/6.1, 714/14
• US Class Current: 1/1
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/1402 Saving, restoring, recovering or retrying
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

A device includes volatile memory; one or more non-volatile memory chips, each of which is for storing data moved from the volatile-memory; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from a primary power source; a controller in communication with the volatile memory and the non-volatile memory, wherein: the controller is programmed to move data from the volatile memory to the non-volatile memory chips upon a loss of power of the primary power source of the volatile memory; and the at least one parameter describing the volatile memory are stored in at least one of the non-volatile memory chips that store the data moved from the volatile memory. In some aspects the at least one parameter includes serial presence detect information.

Claims

1. A memory system comprising:

a plurality of volatile memory devices;

a non-volatile memory system including a non-volatile memory device, the non-volatile memory system configured to store in the non-volatile memory device at least one parameter describing one of the plurality of volatile memory devices;

an interface configured to couple a backup power source to the one of the plurality of volatile memory devices to temporarily provide power upon a loss of power from a primary power source; and

a controller in communication with the one of the plurality of volatile memory devices and the non-volatile memory device, the controller configured to cause the one of the plurality of volatile memory devices to be taken out of a low power mode and to transmit data to the non-volatile memory device upon the loss of power from the primary power source for the one of the plurality of volatile memory devices, and to cause the volatile memory devices that are not transmitting data to enter into the low power mode,

wherein the controller is configured to not transmit data from the one of the plurality of volatile memory devices, during the loss of power, upon receipt of a signal to ignore data in the one of the plurality of volatile memory devices.

2. The memory system of claim 1, wherein the at least one parameter comprises one of serial presence detect information, a size of the one of the plurality of volatile memory devices, or a speed of the one of the plurality of volatile memory devices.

3. The memory system of claim 1, wherein the controller further comprises a cache memory device for storing the at least one parameter.

4. The memory system of claim 1, further comprising a configuration data bus for accessing the at least one parameter.

5. The memory system of claim 1, further comprising a configuration data bus for accessing the at least one parameter, and wherein the controller is further configured retrieve the at least one parameter in response to receiving a request for the at least one parameter over the configuration data bus.

6. The memory system of claim 1, wherein the controller is further configured to cause the non-volatile memory device to transmit data to the one of the plurality of volatile memory devices upon a restoration of power of the primary power source.

7. The memory system of claim 1, wherein the backup power source comprises a capacitor.

8. The memory system of claim 7, wherein the controller is configured to determine a health of the capacitor by measuring an amount of time it takes to fully charge the capacitor.

9. The memory system of claim 1, wherein the data transmitted by the one of the plurality of volatile memory devices comprises directory information that indicates a location of data in a file system of the one of the plurality of volatile memory devices.

10. The memory system of claim 1, wherein when the power of the primary power source returns before the one of the volatile memory devices completes the transmission of the data to the non-volatile memory device, the controller is further configured to enable retrieval of the data directly from the one of the plurality of volatile memory devices.

11. The memory system of claim 1, wherein, upon a loss of power of the primary power source for the plurality of volatile memory devices, the controller is configured to cause each of the plurality of volatile memory devices to transmit data to the non-volatile memory device in a sequential manner.

12. A method comprising:

maintaining at least one parameter describing one of a plurality of volatile memory devices at a non-volatile memory system including a non-volatile memory device;

upon a loss of power of a primary power source at the one of the volatile memory devices;

causing the volatile memory devices not transmitting data to enter into a low power mode; and

causing the one of the volatile memory devices to be taken out of the low power mode and to transmit data to the non-volatile memory system based on the at least one parameter while the one of the volatile memory devices is temporarily powered by a backup power source, thereby causing the non-volatile memory device to store both the data transmitted by the one of the volatile memory devices and the at least one parameter,

wherein the one of the volatile memory devices will not transmit data during the loss of power, when a signal to ignore data, in the one of the plurality of volatile memory devices, is asserted.

13. The method of claim 12, wherein the at least one parameter comprises at least one of serial presence detect information, a size of the one of the volatile memory devices, or a speed of the one of the volatile memory devices.

14. The method of claim 12, further comprising causing the non-volatile memory device to transmit data to the one of the volatile memory devices upon a restoration of power of the primary power source.

15. The method of claim 12, wherein the backup power source comprises a capacitor.

16. The method of claim 15, further comprising determining a health of the capacitor by measuring an amount of time it takes to fully charge the capacitor.

17. The method of claim 12 further comprising storing the data in a plurality of storage devices in the non-volatile memory device.

18. The method of claim 12, further comprising, upon a loss of power of the primary power source for the plurality of volatile memory devices, causing each of the plurality of volatile memory devices to transmit data to the non-volatile memory device in a sequential manner.

19. The method of claim 12, further comprising, when the power of the primary power source returns before the one of the plurality of volatile memory devices completes the transmission of the data to the non-volatile memory device, enabling retrieval of the data directly from the one of the plurality of volatile memory devices.

20. The method of claim 12, further comprising receiving a notification of an imminent power loss through one of an edge connector or an I²C interface.