Semiconductor device having stacked oxide semiconductor layers

• US 9,520,287 B2
• Filed: 06/05/2014
• Issued: 12/13/2016
• Est. Priority Date: 11/28/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US14/296,893
• Publication Number:
  US 20140349443A1
• Time in Patent Office: 922 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02472 Oxides
• CPC Class Codes: H01L 21/02483 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: Y10T 156/10 Methods of surface bonding and/or assembly therefor
• CPC Class Codes: Y10T 428/24174 : including sheet or component perpendicular to plane of web or sheet

Abstract

One embodiment is a method for manufacturing a stacked oxide material, including the steps of forming an oxide component over a base component; forming a first oxide crystal component which grows from a surface toward an inside of the oxide component by heat treatment, and leaving an amorphous component just above a surface of the base component; and stacking a second oxide crystal component over the first oxide crystal component. In particular, the first oxide crystal component and the second oxide crystal component have common c-axes. Same-axis (axial) growth in the case of homo-crystal growth or hetero-crystal growth is caused.

Claims

1. A semiconductor device comprising:

a gate electrode;

a gate insulating film over the gate electrode;

a first oxide semiconductor layer over the gate insulating film;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a third oxide semiconductor layer over the second oxide semiconductor layer; and

a source electrode and a drain electrode electrically connected to the second oxide semiconductor layer,

wherein the second oxide semiconductor layer comprises a channel formation region which overlaps with the gate electrode with the first oxide semiconductor layer and the gate insulating film interposed therebetween, and

wherein the second oxide semiconductor layer comprises crystals which are c-axis-aligned.

2. The semiconductor device according to claim 1, further comprising:

an insulating film over and in contact with the third oxide semiconductor layer; and

a conductive layer over the insulating film,

wherein the gate electrode and the conductive layer overlap with each other with the channel formation region interposed therebetween.

3. The semiconductor device according to claim 1,

wherein the first oxide semiconductor layer comprises an amorphous region.

4. The semiconductor device according to claim 1,

wherein the third oxide semiconductor layer comprises crystals which are c-axis-aligned.

5. The semiconductor device according to claim 1,

wherein the c-axes of the crystals in the second oxide semiconductor layer are aligned perpendicular to a surface of the second oxide semiconductor layer.

6. The semiconductor device according to claim 1,

wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer contains indium and zinc.

7. A semiconductor device comprising:

a gate electrode;

a gate insulating film;

a first oxide semiconductor layer;

a second oxide semiconductor layer;

a third oxide semiconductor layer; and

a source electrode and a drain electrode electrically connected to the second oxide semiconductor layer,

wherein the second oxide semiconductor layer is between the first oxide semiconductor layer and the third oxide semiconductor layer,

wherein the second oxide semiconductor layer comprises a channel formation region,

wherein the gate electrode and the channel formation region overlap with each other with the first oxide semiconductor layer and the gate insulating film interposed therebetween, and

wherein the second oxide semiconductor layer comprises crystals which are c-axis-aligned.

8. The semiconductor device according to claim 7,

wherein the first oxide semiconductor layer comprises an amorphous region.

9. The semiconductor device according to claim 7,

wherein the third oxide semiconductor layer comprises crystals which are c-axis-aligned.

10. The semiconductor device according to claim 7,

wherein the c-axes of the crystals in the second oxide semiconductor layer are aligned perpendicular to a surface of the second oxide semiconductor layer.

11. The semiconductor device according to claim 7,

wherein each of the second oxide semiconductor layer and the third oxide semiconductor layer contains indium, gallium and zinc, and

wherein composition ratio of the second oxide semiconductor layer and the third oxide semiconductor layer are different from each other.

12. The semiconductor device according to claim 7,

wherein a material of the second oxide semiconductor layer and a material of the third oxide semiconductor layer are different from each other.

13. A semiconductor device comprising:

a gate electrode;

a gate insulating film;

an oxide semiconductor layer comprising a first oxide semiconductor layer, a second oxide semiconductor layer over the first oxide semiconductor layer, and a third oxide semiconductor layer over the second oxide semiconductor layer; and

a source electrode and a drain electrode electrically connected to the oxide semiconductor layer,

wherein a relation of E_c−

E_f<

E_g/2 is satisfied where E_c is an energy at a bottom of a conduction band of the oxide semiconductor layer, E_f is a Fermi energy of the oxide semiconductor layer, and E_g is a band gap of the oxide semiconductor layer,

wherein the second oxide semiconductor layer comprises a channel formation region,

wherein the channel formation region and the gate electrode overlap with each other with the gate insulating film and the first oxide semiconductor layer interposed therebetween, and

wherein the second oxide semiconductor layer comprises crystals which are c-axis-aligned.

14. The semiconductor device according to claim 13, further comprising:

an insulating film over and in contact with the third oxide semiconductor layer; and

a conductive layer over the insulating film,

wherein the gate electrode and the conductive layer overlap with each other with the channel formation region interposed therebetween.

15. The semiconductor device according to claim 13,

wherein the first oxide semiconductor layer comprises an amorphous region.

16. The semiconductor device according to claim 13,

wherein the third oxide semiconductor layer comprises crystals which are c-axis-aligned.

17. The semiconductor device according to claim 13,

wherein each of the second oxide semiconductor layer and the third oxide semiconductor layer contains indium, gallium and zinc, and

wherein composition ratio of the second oxide semiconductor layer and the third oxide semiconductor layer are different from each other.

18. The semiconductor device according to claim 13, wherein a material of the second oxide semiconductor layer and a material of the third oxide semiconductor layer are different from each other.