Aging-based leakage energy reduction method and system

• US 9,520,292 B2
• Filed: 01/06/2013
• Issued: 12/13/2016
• Est. Priority Date: 01/06/2013
• Status: Expired due to Fees

• Current Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Original Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Inventors: Potkonjak, Miodrag
• Primary Examiner(s): Cole, Brandon S
• Application Number:
  US14/407,072
• Publication Number:
  US 20150162199A1
• Time in Patent Office: 1,437 Days
• Field of Search: 327524-602
• US Class Current: 1/1
• CPC Class Codes: G06F 2119/04 Ageing analysis or optimisation against ageing
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 21/326 Application of electric currents or fields, e.g. for electroforming H01L21/20 - H01L21/288 and H01L21/302 - H01L21/324 take precedence
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H03K 17/161 in field-effect transistor switches
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption

Abstract

A technique of reducing leakage energy associated with a post-silicon target circuit is generally described herein. One example method includes purposefully aging a plurality of gates in the target circuit based on a targeted metric including a timing constraint associated with the target circuit.

Claims

1. A method to reduce leakage energy associated with a post-silicon target circuit, the method comprising:

selecting a plurality of gates in the target circuit to be aged;

determining an extent to which to age the selected plurality of gates;

identifying a first set of gates and a second set of gates of the selected plurality of gates that will be aged differently based on a targeted metric including a timing constraint associated with the target circuit;

based on the targeted metric, aging, to the determined extent, the first set of gates; and

based on the targeted metric, aging, to less than the determined extent, the second set of gates.

2. The method of claim 1, further comprising characterizing the plurality of gates at a transistor or gate level.

3. The method of claim 1, wherein determining the extent to which to age the selected plurality of gates comprises assigning a first weight and a second weight to each gate in the target circuit based on a contribution of the each gate to energy consumption and critical timing constraints of the target circuit, wherein the first weight is associated with leakage energy, and the second weight is associated with timing.

4. The method of claim 3, further comprising:

formulating a satisfiability (SAT) problem that includes a first set of objectives for the first set of gates and a second set of objectives for the second set of gates to reduce the leakage energy associated with the target circuit; and

selecting a set of candidate input vectors for the target circuit by iteratively solving the SAT problem by removing one or more gates from being considered in the first set of objectives and the second set of objectives based on the first weight and the second weight,

wherein aging to the determined extent the first set of gates and aging to less than the determined extent the second set of gates comprise applying the set of candidate input vectors to the plurality of gates to stress the plurality of gates.

5. The method of claim 4, further comprising selecting a subset of input vectors from the set of candidate input vectors in such a way that the timing constraint associated with the target circuit is also satisfied.

6. The method of claim 5, further comprising setting the timing constraint in a linear program that includes an objective of reducing leakage energy associated with the first set of gates.

7. The method of claim 6, further comprising approximating a possible critical path in the target circuit based on an initial longest path in terms of delays associated with a subset of gates in the target circuit.

8. The method of claim 5, further comprising:

providing the subset of input vectors to the target circuit to age at least some of the first set of gates more than the second set of gates.

9. The method of claim 1, further comprising applying adaptive body bias (ABB) to the target circuit based on the targeted metric.

10. The method of claim 1, wherein aging the plurality of gates in the target circuit reduces a hot spot in the target circuit.

11. The method of claim 1, wherein aging the plurality of gates in the target circuit improves yield.

12. The method of claim 1, wherein aging to the determined extent the first set of gates and aging to less than the determined extent the second set of gates comprises applying a set of candidate input vectors to the plurality of gates to stress the plurality of gates.

13. A non-transitory computer-readable medium that includes instructions to reduce leakage energy associated with a post-silicon target circuit, which in response to execution by a processor, cause the processor to perform or control performance of:

select a plurality of gates in the target circuit to be aged;

determine an extent to which to age the selected plurality of gates;

identify a first set of gates and a second set of gates of the selected plurality of gates that will be aged differently based on a targeted metric including a timing constraint associated with the target circuit;

based on the targeted metric, age, to the determined extent, the first set of gates; and

based on the targeted metric, age, to less than the determined extent, the second set of gates.

14. The non-transitory computer-readable medium of claim 13, further including instructions, which in response to execution by the processor, cause the processor to perform or control performance of characterize the plurality of gates at a transistor or gate level.

15. The non-transitory computer-readable medium of claim 13, further including instructions, which in response to execution by the processor, cause the processor to perform or control performance of:

assign a first weight and a second weight to each gate in the target circuit based on a contribution of the each gate to energy consumption and critical timing constraints of the target circuit, wherein the first weight is associated with leakage energy, and the second weight is associated with timing.

16. The non-transitory computer-readable medium of claim 15, further including instructions, which in response to execution by the processor, cause the processor to perform or control performance of:

formulate a satisfiability (SAT) problem that includes a first set of objectives for the first set of gates and a second set of objectives for the second set of gates to reduce the leakage energy associated with the target circuit; and

select a set of candidate input vectors for the target circuit through an iterative solution of the SAT problem by removal of one or more gates from being considered in the first set of objectives and the second set of objectives based on the first weight and the second weight,

wherein to age to the determined extent the first set of gates and to age to less than the determined extent the second set of gates, the instructions, in response to execution by the processor, cause the processor to perform or control performance of;

apply the set of candidate input vectors to the plurality of gates to stress the plurality of gates.

17. The non-transitory computer-readable medium of claim 16, further including instructions, which in response to execution by the processor, cause the processor to perform or control performance of:

select a subset of input vectors from the set of candidate input vectors in such a way that the timing constraint associated with the target circuit is also satisfied.

18. The non-transitory computer-readable medium of claim 17, further including instructions, which in response to execution by the processor, cause the processor to perform or control performance of:

set the timing constraint in a linear program that includes an objective to reduce leakage energy associated with the first set of gates.

19. The non-transitory computer-readable medium of claim 18, further including instructions, which in response to execution by the processor, cause the processor to perform or control performance of:

approximate a possible critical path in the target circuit based on an initial longest path in terms of delays associated with a subset of gates in the target circuit.

20. The non-transitory computer-readable medium of claim 17, further including instructions, which in response to execution by the processor, cause the processor to perform or control performance of:

provide the subset of input vectors to the target circuit to age at least some of the first set of gates more than the second set of gates.

21. The non-transitory computer-readable medium of claim 13, further including instructions, which in response to execution by the processor, cause the processor to perform or control performance of:

apply adaptive body bias (ABB) to the target circuit based on the targeted metric.

22. The non-transitory computer-readable medium of claim 13, wherein aging of the plurality of gates in the target circuit reduces a hot spot in the target circuit.

23. The non-transitory computer-readable medium of claim 13, wherein the aging of the plurality of gates in the target circuit improves yield.

24. The non-transitory computer-readable medium of claim 13, wherein to age to the determined extent the first set of gates and to age to less than the determined extent the second set of gates, the instructions, in response to execution by the processor, cause the processor to perform or control performance of:

apply a set of candidate input vectors to the plurality of gates to stress the plurality of gates.

25. A computing device coupled to a post-silicon target circuit and configured to reduce leakage energy associated with the post-silicon target circuit, comprising:

a programmable unit; and

a processor, coupled to the programmable unit, wherein the processor is configured to;

select a plurality of gates in the target circuit to be aged;

determine an extent to which to age the selected plurality of gates;

identify a first set of gates and a second set of gates of the selected plurality of gates that will be aged differently based on a targeted metric including a timing constraint associated with the target circuit;

based on the targeted metric, age, to the determined extent, the first set of gates; and

based on the targeted metric, age, to less than the determined extent, the second set of gates.

26. The computing device of claim 25, wherein the processor is further configured to characterize the plurality of gates at a transistor or gate level.

27. The computing device of claim 25, wherein the processor is further configured to:

assign a first weight and a second weight to each gate in the target circuit based on a contribution of the each gate to energy consumption and critical timing constraints of the target circuit, wherein the first weight is associated with leakage energy, and the second weight is associated with timing.

28. The computing device of claim 27, wherein the processor is further configured to:

formulate a satisfiability (SAT) problem that includes a first set of objectives for the first set of gates and a second set of objectives for the second set of gates to reduce the leakage energy associated with the target circuit; and

select a set of candidate input vectors for the target circuit through an iterative solution of the SAT problem by removal of one or more gates from being considered in the first set of objectives and the second set of objectives based on the first weight and the second weight,

wherein to age to the determined extent the first set of gates and to age to less than the determined extent the second set of gates, the processor is configured to apply the set of candidate input vectors to the plurality of gates to stress the plurality of gates.

29. The computing device of claim 28, wherein the processor is configured to select a subset of input vectors from the set of candidate input vectors in such a way that the timing constraint associated with the target circuit is also satisfied.

30. The computing device of claim 29, wherein the processor is further configured to set the timing constraint in a linear program that includes an objective to reduce leakage energy associated with the first set of gates.

31. The computing device of claim 30, wherein the processor is further configured to approximate a possible critical path in the target circuit based on an initial longest path in terms of delays associated with a subset of gates in the target circuit.

32. The computing device of claim 29, wherein the processor is further configured to load the subset of input vectors in the programmable unit, so that the subset of input vectors are applied to the target circuit to age at least some of the first set of gates more than the second set of gates.

33. The computing device of claim 25, wherein the processor is further configured to apply adaptive body bias (ABB) to the target circuit based on the targeted metric.

34. The computing device of claim 25, wherein to age to the determined extent the first set of gates and to age to less than the determined extent the second set of gates, the processor is configured to apply a set of candidate input vectors to the plurality of gates to stress the plurality of gates.