Semiconductor device having a low divot of alignment between a substrate and an isolation thereof and method of forming the same

• US 9,520,296 B2
• Filed: 06/12/2014
• Issued: 12/13/2016
• Est. Priority Date: 06/12/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, De-Fang, Tsai, Teng-Chun, Lin, Cheng-Tung, Wang, Li-Ting, Peng, Chih-Tang
• Primary Examiner(s): Dickey, Thomas L
• Assistant Examiner(s): Yi, Changhyun
• Application Number:
  US14/302,568
• Publication Number:
  US 20150364333A1
• Time in Patent Office: 915 Days
• Field of Search: 257/369, 257/E21.632, 257/E27.062, 438/231
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

According to an exemplary embodiment, a method of forming vertical structures is provided. The method includes the following operations: providing a substrate; forming a first oxide layer over the substrate; forming a first dummy layer over the first oxide layer; etching the first oxide layer and the first dummy layer to form a recess; forming a second dummy layer in the recess (and further performing CMP on the second dummy layer and stop on the first dummy layer); removing the first dummy layer; removing the first oxide layer; and etching the substrate to form the vertical structure. According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes: a substrate; an STI embedded in the substrate; and a vertical transistor having a source substantially aligned with the STI.

Claims

1. A method of forming vertical structures, comprising:

providing a substrate;

forming a first oxide layer over the substrate;

forming a shallow trench isolation to divide the substrate into a first region and a second region;

forming a first dummy layer over the first oxide layer and the shallow trench isolation;

etching the first oxide layer and the first dummy layer to form a first recess in the first region and a second recess in the second region;

forming a second dummy layer in the first recess and the second recess;

removing the first dummy layer;

removing the first oxide layer;

etching a portion of the shallow trench isolation; and

etching the substrate to make the substrate aligned with a top of the shallow trench isolation and to form a first vertical structure in the first region and a second vertical structure in the second region.

2. The method of claim 1, wherein forming the first oxide layer over the substrate further comprises forming the first oxide layer made of silicon oxide over the substrate.

3. The method of claim 1, wherein forming the first dummy layer over the first oxide layer and the shallow trench isolation further comprises forming the first dummy layer made of conductive material over the first oxide layer and the shallow trench isolation.

4. The method of claim 1, wherein forming the first dummy layer over the first oxide layer and the shallow trench isolation further comprises forming the first dummy layer made of dielectric material over the first oxide layer and the shallow trench isolation.

5. The method of claim 1, wherein forming the second dummy layer in the first recess and the second recess further comprises forming the second dummy layer of high etch selectivity toward the first dummy layer.

6. The method of claim 1, wherein forming the second dummy layer in the first recess and the second recess further comprises forming the second dummy layer made of SiOCN in the first recess and the second recess.

7. The method of claim 1, wherein etching the substrate to make the substrate aligned with the top of the shallow trench isolation and to form the first vertical structure in the first region and the second vertical structure in the second region further comprises etching the substrate to make a divot between the top of the shallow trench isolation and the substrate lower than 20-100 angstroms.

8. The method of claim 1, further comprising performing chemical mechanical polishing on the second dummy layer and stopping at the first dummy layer.

9. The method of claim 1, further comprising:

performing hydrogen annealing on the first vertical structure, the second vertical structure, and the substrate;

performing an in-situ steam generation process on the first vertical structure, the second vertical structure, and the substrate to form a third oxide layer;

performing STI densification annealing on the shallow trench isolation;

etching the third oxide layer while maintain the shallow trench isolation;

forming a screen oxide on the first vertical structure, the second vertical structure, and the substrate;

ion implanting a first dopant into the first region of the substrate through the screen oxide;

ion implanting a second dopant into the second region of the substrate through the screen oxide; and

removing the screen oxide.

10. The method of claim 1, wherein forming the shallow trench isolation to divide the substrate into the first region and the second region further comprises:

forming a stop layer over the first oxide layer;

forming a second oxide layer over the stop layer;

forming a planarization layer over the second oxide layer;

etching the first oxide layer, the stop layer, the second oxide layer, and the planarization layer to expose a portion of the substrate;

removing the planarization layer;

removing the second oxide layer;

etching the exposed portion of the substrate to form a trench;

forming a third oxide layer in the trench;

polishing the third oxide layer and stopping at the stop layer; and

removing the stop layer.

11. A method of forming a vertical structure, comprising:

providing a substrate;

forming a first oxide layer over the substrate;

forming a first dummy layer over the first oxide layer;

etching the first oxide layer and the first dummy layer to form a recess;

forming a second dummy layer in the recess;

removing the first dummy layer;

removing the first oxide layer; and

etching the substrate to form the vertical structure.

12. The method of claim 11, wherein forming the first oxide layer over the substrate further comprises forming the first oxide layer made of silicon oxide over the substrate.

13. The method of claim 11, wherein forming the first dummy layer over the first oxide layer further comprises forming the first dummy layer made of conductive material over the first oxide layer.

14. The method of claim 11, wherein forming the first dummy layer over the first oxide layer further comprises forming the first dummy layer made of dielectric material over the first oxide layer.

15. The method of claim 11, wherein forming the second dummy layer in the recess further comprises forming the second dummy layer of high etch selectivity toward the first dummy layer.

16. The method of claim 11, wherein forming the second dummy layer in the recess further comprises forming the second dummy layer made of SiOCN in the recess.

17. The method of claim 11, further comprising:

performing chemical mechanical polishing on the second dummy layer and stopping at the first dummy layer.