Thin film transistor panel having an etch stopper on semiconductor

• US 9,520,412 B2
• Filed: 07/13/2015
• Issued: 12/13/2016
• Est. Priority Date: 02/11/2010
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Yun, Pil-Sang, Kim, Ki-Won, Ryu, Hye-Young, Lee, Woo-Geun, Choi, Seung-Ha, Youn, Jae-Hyoung, Chung, Kyoung-Jae, Lee, Young-Wook, Lee, Je-Hun, Yoon, Kap-Soo, Kim, Do-Hyun, Yang, Dong-Ju, Choi, Young-Joo
• Primary Examiner(s): Pham, Hoai V
• Application Number:
  US14/798,123
• Publication Number:
  US 20150318317A1
• Time in Patent Office: 519 Days
• Field of Search: 438/149, 438/151
• US Class Current: 1/1
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/465 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/469
• CPC Class Codes: H01L 21/475 using masks
• CPC Class Codes: H01L 21/47573 Etching the layer
• CPC Class Codes: H01L 21/47635 After-treatment of these layers
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Claims

1. A method for forming a panel comprising a thin film transistor, the method comprising:

forming an oxide semiconductor pattern comprising a channel region;

forming an etch stopper at a position corresponding to the channel region; and

forming a first electrode and a second electrode spaced apart from the first electrode, the channel region configured to connect the first electrode to the second electrode,

wherein the oxide semiconductor pattern, the first electrode, and the second electrode are formed using a first mask, and

wherein a work function of at least one of the first electrode and the second electrode is lower than a work function of the oxide semiconductor pattern.

2. The method of claim 1, further comprising:

disposing a first conductive layer on a substrate;

disposing a first insulating layer on the first conductive layer;

disposing an oxide semiconductor layer on the first insulating layer;

disposing a second conductive layer on the etch stopper and the oxide semiconductor layer;

wherein the oxide semiconductor layer and the second conductive layer are patterned using the first mask to form the oxide semiconductor pattern, the first electrode, and the second electrode.

3. The method of claim 2, further comprising:

forming a second insulating layer on the first electrode and the second electrode;

patterning the second insulating layer to form a contact hole exposing the first electrode; and

forming a third conductive layer on the second insulating layer;

patterning the third conductive layer to form a third electrode,

wherein the third electrode is connected to the first electrode via the contact hole.

4. The method of claim 3, wherein the second insulating layer comprises a passivation layer.

5. The method of claim 3, wherein the second insulating layer comprises a color filter.

6. The method of claim 3, further comprising:

patterning the first conductive layer to form a fourth electrode, the fourth electrode being disposed under the etch stopper and the oxide semiconductor pattern.

7. The method of claim 6, wherein forming the etch stopper comprises disposing an etch stopper layer on the oxide semiconductor layer and patterning the etch stopper layer.

8. The method of claim 7, wherein the etch stopper is formed by dry etching the etch stopper layer.

9. The method of claim 7, wherein the first conductive layer is patterned using a second mask, the etch stopper layer is patterned using a third mask, the second insulating layer is patterned using a fourth mask, and the third conductive layer is patterned using a fifth mask.

10. The method of claim 2, wherein the oxide semiconductor pattern, the first electrode, and the second electrode are formed by wet etching the second conductive layer and the oxide semiconductor layer.