Oxide thin film transistor and manufacturing method thereof, array substrate and display device

• US 9,520,422 B2
• Filed: 11/03/2014
• Issued: 12/13/2016
• Est. Priority Date: 11/05/2013
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Choi, Hyun Sic, Im, Yun Sik
• Primary Examiner(s): Kim, Jay C
• Application Number:
  US14/652,639
• Publication Number:
  US 20150340504A1
• Time in Patent Office: 771 Days
• Field of Search: 257/43
• US Class Current: 1/1
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/467 using masks
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An oxide thin film transistor and a manufacturing method thereof, an array substrate and a display device are provided. The method comprises: forming a gate electrode (1), a gate insulating layer (4) and an oxide semiconductor thin film (10) sequentially on a substrate; forming a first photoresist (11a) above an active layer region of the oxide semiconductor thin film (10), such that a thickness of the first photoresist above a channel region is greater than a thickness of the first photoresist above a non-channel region; reserving the first photoresist (11a) above the channel region; forming a source-drain metal thin film and a second photoresist (11b) sequentially on a pattern of an active layer, removing a portion of the source-drain metal thin film and a portion of the second photoresist (11b), such that an edge of the first photoresist (11a) above the channel region is covered with the source-drain metal thin film; and obtaining patterns of a source electrode and a drain electrode. Upon preliminary patterns of the source electrode and the drain electrode are formed, the photoresist instead of a protective layer is used to protect the active layer, therefore shortening a length of a channel of the oxide thin film transistor.

Claims

1. A manufacturing method of an oxide thin film transistor, comprising:

forming a gate electrode and a gate insulating layer sequentially on a substrate;

forming an oxide semiconductor thin film on the gate insulating layer, and forming a first photoresist above an active layer region of the oxide semiconductor thin film, wherein a thickness of a portion of the first photoresist above a channel region is greater than a thickness of a portion of the first photoresist above a non-channel region;

removing a non-active layer region of the oxide semiconductor thin film to form a pattern of an active layer, removing the portion of the first photoresist above the non-channel region, and reserving the portion of the first photoresist above the channel region;

forming a source-drain metal thin film and a second photoresist sequentially on the pattern of the active layer, removing part of a portion of the source-drain metal thin film corresponding to the portion of the first photoresist above the channel region and part of a portion of the second photoresist corresponding to the portion of the first photoresist above the channel region, such that an edge of the portion of the first photoresist above the channel region is covered by a portion of the remaining source-drain metal thin film; and

lifting off the remaining second photoresist, removing the portion of the remaining source-drain metal thin film covering the edge of the portion of the first photoresist above the channel region, and lifting off the portion of the first photoresist above the channel region to form patterns of a source electrode and a drain electrode.

2. The method according to claim 1, wherein a photoresist is formed on the oxide semiconductor thin film;

a portion of the photoresist above the non-active layer region is fully fully-transparently exposed and developed, a portion of the photoresist above the non-channel region of the active layer region is partially exposed and developed, and a portion of the photoresist above the channel region is non-transparently exposed and developed by half-tone mask to form the first photoresist above the active layer region.

3. The method according to claim 2, wherein the non-active layer region of the oxide semiconductor thin film is removed by a patterning process to obtain the pattern of the active layer;

and the portion of the first photoresist above the non-channel region is removed by an ashing process to reserve the portion of the first photoresist above the channel region.

4. The method according to claim 1, wherein a length of a channel in the oxide thin film transistor is in a range of 5 μ

m to 7 μ

m.

5. The method according to claim 4, wherein the length of the channel in the oxide thin film transistor is in a range of 5 μ

m to 6 μ

m.

6. The method according to claim 2, wherein a length of a channel in the oxide thin film transistor is in a range of 5 μ

m to 7 μ

m.

7. The method according to claim 6, wherein the length of the channel in the oxide thin film transistor is in a range of 5 μ

m to 6 μ

m.

8. The method according to claim 3, wherein a length of a channel in the oxide thin film transistor is in a range of 5 μ

m to 7 μ

m.

9. The method according to claim 8, wherein the length of the channel in the oxide thin film transistor is in a range of 5 μ

m to 6 μ

m.