Growth of cubic crystalline phase strucure on silicon substrates and devices comprising the cubic crystalline phase structure

• US 9,520,472 B2
• Filed: 03/15/2013
• Issued: 12/13/2016
• Est. Priority Date: 05/04/2012
• Status: Active Grant

• Current Assignee: Rensselaer Polytechnic Institute
• Original Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Inventors: Wetzel, Christian, Lee, Seung-Chang, Brueck, Steven R. J., Stark, Christoph, Detchprohm, Theeradetch
• Primary Examiner(s): GHYKA, ALEXANDER G
• Application Number:
  US14/383,833
• Publication Number:
  US 20150108427A1
• Time in Patent Office: 1,369 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02494 Structure
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02549 Antimonides
• CPC Class Codes: H01L 21/02587 Structure
• CPC Class Codes: H01L 21/02598 monocrystalline
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 29/15 Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices such structures applied for the control of light G02F1/017, applied in semiconductor lasers H01S5/34
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 33/16 with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
• CPC Class Codes: H01L 33/24 of the light emitting region, e.g. non-planar junction

Abstract

A semiconductor device is disclosed. The semiconductor device includes a substrate comprising a groove. A buffer layer is formed on a surface of the groove. The buffer layer comprising at least one material chosen from AIN, GaN or Al_xGa_1-xN, where x is between zero and one. An epitaxially grown semiconductor material is disposed over the buffer layer, at least a portion of the epitaxially grown semiconductor material having a cubic crystalline phase structure. Methods of forming the semiconductor devices are also taught.

Claims

1. A semiconductor device comprising:

a (001) crystalline semiconductor substrate comprising a groove exposing (111) faces of crystalline semiconductor;

a buffer layer formed on a surface of the groove, the buffer layer comprising at least one material chosen from AlN, GaN or Al_xGa_1-xN, where x is between zero and one; and

an epitaxially grown semiconductor material disposed over the buffer layer, the epitaxially grown semiconductor material having a cubic crystalline phase structure and a hexagonal phase structure, wherein the epitaxially grown semiconductor layer includes at least one quantum well spanning and disposed in both the cubic crystalline phase structure and the hexagonal phase structure.

2. The semiconductor device of claim 1, wherein the groove is a v-groove.

3. The semiconductor device of claim 2, wherein the width of the v-groove is less than about 10 micrometers.

4. The semiconductor device of claim 1, wherein the substrate comprises (001) single crystal silicon.

5. The semiconductor device of claim 1, wherein the buffer layer comprises an AlN nucleation layer and an Al_xGa_1-xN interlayer deposited on the nucleation layer, where x is defined as in claim 1.

6. The semiconductor device of claim 5, wherein a concentration of Al and Ga in the interlayer is graded through at least a portion of the thickness of the interlayer.

7. The semiconductor device of claim 5, wherein a concentration of Al and Ga in the interlayer is substantially constant through the thickness of the interlayer.

8. The semiconductor device of claim 5, wherein a concentration of Al and Ga varies in a stepwise manner through at least a portion of the thickness of the interlayer.

9. The semiconductor device of claim 1, wherein the epitaxially grown semiconductor material includes a spatially continuous, phase-separated cubic Ill-nitride material along the length of the groove.

10. The semiconductor device of claim 1, wherein the epitaxially grown semiconductor material further comprises c-In_yGa_1-yN, where y is greater than zero and equal to or less than one.

11. The semiconductor device of claim 1, wherein the epitaxially grown semiconductor material includes at least one quantum well.

12. The semiconductor device of claim 1, wherein the substrate comprises a plurality of grooves and the epitaxially grown semiconductor material comprises a plurality of separated cubic regions formed in the grooves.

13. The semiconductor device of claim 1, wherein the epitaxially grown semiconductor material comprises a c-GaN region and a h-GaN region.

14. The semiconductor device of claim 1, wherein the device is an LED, a transistor, a photodetector or a laser.

15. The semiconductor device of claim 1, wherein the semiconductor device comprises stripes of the epitaxially grown layer and silicon regions, wherein electronic devices are positioned in both the epitaxially grown layer and the silicon regions.

16. A method of forming a semiconductor device, the method comprising:

providing a planar crystalline substrate comprising a groove exposing different crystal faces than the planar surface;

depositing a buffer layer over the substrate, the buffer layer comprising at least one material chosen from AlN, GaN or Al_xGa_1-xN, where x is between zero and one;

epitaxially growing a semiconductor layer over the buffer layer, the epitaxially grown semiconductor layer having a cubic crystalline phase structure and a hexagonal phase structure, wherein the epitaxially grown semiconductor layer includes at least one quantum well spanning and disposed in both the cubic crystalline phase structure and the hexagonal phase structure.

17. The method of claim 16, further comprising removing at least a portion of the substrate and bonding the remaining portion comprising the epitaxially grown layer to a second substrate.

18. The method of claim 16, wherein selective area decomposition of a precursor gas is used to form electrical connections to the cubic crystalline devices.

19. The method of claim 16, wherein the method comprises completely or partially removing at least one of Si material from the substrate, or h-GaN or h-InGaN quantum wells from the epitaxially grown layer.

20. A method of forming a semiconductor device, the method comprising:

providing a planar crystalline substrate comprising a groove exposing different crystal faces than the planar surface;

depositing a buffer layer over the substrate, the buffer layer comprising at least one material chosen from MN, GaN or Al_xGa_1-xN, where x is between zero and one;

epitaxially growing a semiconductor layer over the buffer layer, the epitaxially grown semiconductor layer having a cubic crystalline phase structure and a hexagonal phase structure, wherein the epitaxially grown semiconductor layer includes at least one quantum well spanning both the cubic crystalline phase structure and the hexagonal phase structure;

providing a handle wafer;

bonding the epitaxially grown semiconductor layer to the handle wafer;

removing the substrate; and

removing the hexagonal phase structure from the cubic crystalline phase structure.