Methods of forming a semiconductor device with a gate stack having tapered sidewalls

• US 9,520,474 B2
• Filed: 09/12/2013
• Issued: 12/13/2016
• Est. Priority Date: 09/12/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Che-Cheng, Chen, Chang-Yin, Chen, Yi-Jen, Chang, Yung Jung
• Primary Examiner(s): Armand, Marc
• Assistant Examiner(s): Boulghassoul, Younes
• Application Number:
  US14/024,848
• Publication Number:
  US 20150069535A1
• Time in Patent Office: 1,188 Days
• Field of Search: 257/412, 257/346, 257/387, 257/369, 438/302, 438/591, 438/285, 438/287, 438/283, 438/303, 438/301
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided.

Claims

1. A method of forming a semiconductor device, comprising:

forming a gate dielectric;

forming a silicon dummy layer over the gate dielectric;

performing a first etch using a first etch chemistry to etch through a first portion of the silicon dummy layer;

performing a second etch using a second etch chemistry to etch through a second portion of the silicon dummy layer, the second etch chemistry different than the first etch chemistry;

performing a third etch using a third etch chemistry to concurrently etch through a third portion of the silicon dummy layer and a portion of the gate dielectric to taper a sidewall of the gate dielectric and a sidewall of the silicon dummy layer such that a top surface length of a top surface of the silicon dummy layer is not equal to a bottom surface length of a bottom surface of the silicon dummy layer and a top surface length of a top surface of the gate dielectric is not equal to a bottom surface length of a bottom surface of the gate dielectric; and

replacing the silicon dummy layer with a metal gate electrode.

2. The method of claim 1, comprising etching through a photoresist layer before forming the gate dielectric.

3. The method of claim 2, comprising removing a BARC layer after etching through the photoresist layer.

4. The method of claim 3, comprising removing a bottom layer after removing the BARC layer.

5. The method of claim 1, wherein the second etch tapers a first portion of the sidewall of the silicon dummy layer and the third etch tapers a second portion of the sidewall of the silicon dummy layer.

6. The method of claim 1, wherein the third etch is stopped when the sidewall of the gate dielectric and the sidewall of the silicon dummy layer lie in a same plane.

7. The method of claim 1, comprising forming a cap layer over the gate dielectric before the forming a silicon dummy layer.

8. A method of forming a semiconductor device, comprising:

performing a first etch process to etch through a first portion of a silicon dummy layer;

performing a second etch process to etch through a second portion of the silicon dummy layer, wherein the second etch process tapers a first portion of a sidewall of the silicon dummy layer; and

performing a third etch process to etch through a third portion of the silicon dummy layer, wherein;

the third etch process further etches a portion of a gate dielectric underlying the silicon dummy layer,

the third etch process tapers a second portion of the sidewall of the silicon dummy layer different than the first portion of the sidewall, and

the first portion of the sidewall and the second portion of the sidewall together define a tapered sidewall of the silicon dummy layer;

forming a sidewall spacer adjacent the tapered sidewall of the silicon dummy layer, wherein a sidewall of the sidewall spacer conforms to the tapered sidewall of the silicon dummy layer; and

replacing the silicon dummy layer with a metal gate electrode, wherein a sidewall of the metal gate electrode conforms to the sidewall of the sidewall spacer.

9. The method of claim 8, the first etch process comprising a first flow rate of Cl₂ and the second etch process comprising a second flow rate of Cl₂ different than the first flow rate of Cl₂.

10. The method of claim 8, the first etch process comprising a first flow rate of CF₄ and the second etch process comprising a second flow rate of CF₄ different than the first flow rate of CF₄.

11. The method of claim 10, the third etch process comprising a third flow rate of CF₄ different than the first flow rate of CF₄ and different than the second flow rate of CF₄.

12. The method of claim 8, the third etch process comprising CHF₃.

13. The method of claim 8, wherein the portion of the gate dielectric comprises a sidewall of the gate dielectric and the third etch process tapers the sidewall of the gate dielectric to define a tapered sidewall of the gate dielectric.

14. The method of claim 13, wherein the third etch process is stopped when the sidewall of the gate dielectric and the sidewall of the silicon dummy layer lie in a same plane.

15. The method of claim 8, comprising:

forming a capping layer over the gate dielectric; and

forming the silicon dummy layer over the capping layer.

16. The method of claim 15, wherein the third etch process further etches a portion of the capping layer.

17. A method of forming a semiconductor device, comprising:

forming a gate dielectric;

forming a capping layer over the gate dielectric;

forming a silicon dummy layer over the capping layer;

performing a first etch process to etch through a first portion of the silicon dummy layer;

performing a second etch process to etch through a second portion of the silicon dummy layer, the second etch process different than the first etch process;

performing a third etch process to concurrently etch through a third portion of the silicon dummy layer and a portion of the capping layer to taper a sidewall of the capping layer and a sidewall of the silicon dummy layer; and

replacing the silicon dummy layer with a metal gate electrode.

18. The method of claim 17, wherein the third etch process further etches a portion of the aate dielectric.

19. The method of claim 17, the first etch process comprising a first flow rate of Cl₂ and the second etch process comprising a second flow rate of Cl₂ different than the first flow rate of Cl₂.

20. The method of claim 17, the first etch process comprising a first flow rate of CF₄ and the second etch process comprising a second flow rate of CF₄ different than the first flow rate of CF₄.