Selective body bias for charge pump transfer switches

• US 9,520,776 B1
• Filed: 01/06/2016
• Issued: 12/13/2016
• Est. Priority Date: 09/18/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Reddy, Gooty Sukumar, Yadala, Sridhar
• Primary Examiner(s): Tra, Quan
• Application Number:
  US14/989,666
• Time in Patent Office: 342 Days
• Field of Search: 327/536
• US Class Current: 1/1
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/075 including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages

Abstract

Techniques are presented for improving the efficiencies of multi-stage charge pumps by reducing the amount of voltage lost across the inter-stage transfer switches of the pump through use a selective body bias. The voltage level from both branches of one stage is each supplied though a corresponding diode to the bulk connection of the transfer switch after the subsequent stage in both branches. This arrangement results in each stage providing a largely uniform amount of gain, without the usual increase of voltage drop with increasing numbers of stages.

Claims

1. A charge pump, comprising:

first and second branches connected in parallel between a supply node and an output node, wherein each of the branches includes a plurality of stages connected in series, the first of which is connected to the supply node though a respective initial switch, each stage having;

a stage capacitor;

a stage node connected to the corresponding stage capacitor; and

a transfer switch, through which the corresponding stage node is connected to the stage node of the subsequent stage in the series, except for the final stage of the series, whose stage node is connected through the corresponding transfer switch to the output node,

wherein, when the charge pump is enabled, even and odd stages in the series of the first branch are respectively connected to receive first and second clock non-overlapping clock signals and even and odd stages in the series of the second branch are respectively connected to receive the second and first clock signals; and

first and second diodes through which the stage node of a first one of the stages in the series of both of the first and second branches are respectively connected to provide, for both of the first and second branches, a body bias of the transfer switches of the stage subsequent to the first one of the stages.

2. The charge pump of claim 1, wherein the transfer switches are transistor connected diodes having a gate connected to the corresponding stage node and the initial switches are diode connected transistors having a gate connected to the supply node.

3. The charge pump of claim 1, wherein for each of the stage capacitors, a first plate is connected to the corresponding stage node and a second plate is connected to receive the first clock signal for even stages of the first branch and odd stages of the second branch and to receive the second clock signal for odd stages of the first branch and even stages of the second branch.

4. The charge pump of claim 1, wherein the diodes are high threshold voltage devices.

5. The charge pump of claim 1, wherein the charge pump is formed on a non-volatile memory integrated circuit.

6. The charge pump of claim 5, wherein the charge pump generates programming voltages for use on the non-volatile memory integrated circuit.

7. The charge pump of claim 5, wherein the charge pump generates erase voltages for use on the non-volatile memory integrated circuit.

8. The charge pump of claim 5, wherein the charge pump generates sensing voltages for use on the non-volatile memory integrated circuit.

9. The charge pump of claim 5, wherein the non-volatile memory integrated circuit is a monolithic three-dimensional semiconductor memory device in which memory cells are arranged in multiple physical levels above a silicon substrate and word lines run in a horizontal direction relative to the substrate.

10. The charge pump of claim 1, wherein the first one of the stages in the series is the first stage of the series.

11. The charge pump of claim 1, wherein the first one of the stages in the series is the next to last stage in the series.

12. An integrated circuit, comprising:

an array of non-volatile memory cells;

read, write, and erase circuitry connected to the array; and

a charge pump, comprising;

first and second branches connected in parallel between a supply node and an output node connectable to supply the read, write, and erase circuitry, wherein each of the branches includes a plurality of stages connected in series, the first of which is connected to the supply node though a respective initial switch, each stage having;

a stage capacitor;

a stage node connected to the corresponding stage capacitor;

first and second diodes; and

a transfer switch, through which the corresponding stage node is connected to the stage node of the subsequent stage in the series, except for the final stage of the series, whose stage node is connected through the corresponding transfer switch to the output node,

wherein, when the charge pump is enabled, even and odd stages in the series of the first branch are respectively connected to receive first and second clock non-overlapping clock signals and even and odd stages in the series of the second branch are respectively connected to receive the second and first clock signals, and

wherein the first and second diodes are connected through the stage node of a first one of the stages in the series of both of the first and second branches are respectively connected, for both of the first and second branches, to bias the body of the transfer switches of the stage subsequent to the first one of the stages.

13. The integrated circuit of claim 12, wherein the transfer switches are transistor connected diodes having a gate connected to the corresponding stage node and the initial switches are diode connected transistors having a gate connected to the supply node.

14. The integrated circuit of claim 12, wherein for each of the stage capacitors, a first plate is connected to the corresponding stage node and a second plate is connected to receive the first clock signal for even stages of the first branch and odd stages of the second branch and to receive the second clock signal for odd stages of the first branch and even stages of the second branch.

15. The integrated circuit of claim 12, wherein the integrated circuit is a monolithic three-dimensional semiconductor memory device in which memory cells are arranged in multiple physical levels above a silicon substrate and word lines run in a horizontal direction relative to the substrate.

16. The integrated circuit of claim 12, wherein the first one of the stages in the series is the first stage of the series.

17. The integrated circuit of claim 12, wherein the first one of the stages in the series is the next to last stage in the series.

18. The integrated circuit of claim 12, wherein the charge pump generates programming voltages for the array.

19. The integrated circuit of claim 12, wherein the charge pump generates erase voltages for the array.

20. The integrated circuit of claim 12, wherein the charge pump generates sensing voltages for the array.