Tunable capacitor integrated on one semiconductor die or on one module

• US 9,520,854 B2
• Filed: 08/29/2013
• Issued: 12/13/2016
• Est. Priority Date: 04/03/2012
• Status: Active Grant

• Current Assignee: HiDeep Inc.
• Original Assignee: HiDeep Inc.
• Inventors: Kim, Bonkee, Cho, Youngho, Im, Donggu, Kim, Bumkyum
• Primary Examiner(s): Fureman, Jared
• Assistant Examiner(s): Warmflash, Michael
• Application Number:
  US14/013,235
• Publication Number:
  US 20140002208A1
• Time in Patent Office: 1,202 Days
• Field of Search: 307/109, 361/277
• US Class Current: 1/1
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03H 11/28 Impedance matching networks
• CPC Class Codes: H03H 7/38 Impedance-matching networks

Abstract

Disclosed is a tunable capacitor. The tunable capacitor according to a first embodiment of the present invention includes: a first capacitor; and a switching transistor which switches on/off the connection of the first capacitor between the first terminal and the second terminal, wherein an on/off operation of the switching transistor is performed by a high signal H and a low signal L. The tunable capacitor according to a second embodiment of the present invention includes: a first capacitor; and a switching transistor which switches on/off the connection of the first capacitor between the first terminal and the second terminal, wherein an on/off operation of the switching transistor is performed by a high signal H and a low signal L, and wherein the tunable capacitor is integrated on one semiconductor die or on one module.

Claims

1. A tunable capacitor comprising:

a first capacitor;

a switching transistor which switches on/off a connection of the first capacitor between a first terminal and a second terminal; and

a converter configured to convert a signal applied to a gate terminal G of the switching transistor and apply the converted signal to a drain terminal D and a source terminal S of the switching transistor,

wherein an on/off operation of the switching transistor is performed by a high signal H and a low signal L.

2. The tunable capacitor of claim 1, wherein when the switching transistor is in an on-state, a high signal H is applied to the gate terminal G, and a low signal L is applied to a body terminal B, the drain terminal D and the source terminal S, and wherein when the switching transistor is in an off-state, the low signal L is applied to the gate terminal G and the body terminal B, and the high signal H is applied to the drain terminal D and the source terminal S.

3. The tunable capacitor of claim 1, wherein the switching transistor is a stacked transistor formed by connecting in series a plurality of transistors.

4. The tunable capacitor of claim 1, wherein the gate terminal G and a body terminal B of the switching transistor are connected in series to a resistance respectively.

5. The tunable capacitor of claim 1, wherein the first capacitor is formed by connecting in series or in parallel a plurality of capacitors.

6. A tunable capacitor array comprising a plurality of the tunable capacitors according to claim 1, wherein the plurality of the tunable capacitors are connected in parallel to each other.

7. A tunable capacitor array comprising a plurality of the tunable capacitors according to claim 1, wherein the plurality of the tunable capacitors are connected in parallel to each other.

8. The tunable capacitor array of claim 6, wherein an equivalent capacitance of the plurality of the tunable capacitors is 2^m-1×

C1 (here, m is a natural number less than or equal to n), wherein channel width-to-length ratios W/L of the switching transistors of the plurality of the tunable capacitors are 2^m-1×

W1 (here, m is a natural number less than or equal to n) respectively, and wherein the n is a number of the tunable capacitors, wherein the C1 is an equivalent capacitance of a particular tunable capacitor, and wherein the W1 is a channel width-to-length ratio W/L of the switching transistor.

9. The tunable capacitor array of claim 6, further comprising a fixed capacitor which is connected in parallel to a plurality of the tunable capacitors.

10. The tunable capacitor array of claim 8, further comprising a fixed capacitor which is connected in parallel to a plurality of the tunable capacitors.

11. The tunable capacitor array of claim 6, further comprising a controller which receives a digital control signal and controls on/off of the switching transistor.

12. The tunable capacitor array of claim 8, further comprising a controller which receives a digital control signal and controls on/off of the switching transistor.

13. A tunable capacitor comprising:

a first capacitor;

a switching transistor which switches on/off a connection of the first capacitor between a first terminal and a second terminal; and

a converter configured to convert a signal applied to a gate terminal G of the switching transistor and apply the converted signal to a drain terminal D and a source terminal S of the switching transistor,

wherein an on/off operation of the switching transistor is performed by a high signal H and a low signal L, and wherein the tunable capacitor is integrated on one semiconductor die or on one module.

14. The tunable capacitor of claim 13, wherein when the switching transistor is in an on-state, a high signal H is applied to the gate terminal G, and a low signal L is applied to a body terminal B, the drain terminal D and the source terminal S, and wherein when the switching transistor is in an off-state, the low signal L is applied to the gate terminal G and the body terminal B, and the high signal H is applied to the drain terminal D and the source terminal S.

15. The tunable capacitor of claim 13, wherein the switching transistor is a stacked transistor formed by connecting in series a plurality of transistors.

16. The tunable capacitor of claim 13, wherein the gate terminal G and a body terminal B of the switching transistor are connected in series to a resistance respectively.

17. The tunable capacitor of claim 13, wherein the first capacitor is formed by connecting in series or in parallel a plurality of capacitors.

18. A tunable capacitor array comprising a plurality of the tunable capacitors according to claim 13, wherein the plurality of the tunable capacitors are connected in parallel to each other.

19. A tunable capacitor array comprising a plurality of the tunable capacitors according to claim 13, wherein the plurality of the tunable capacitors are connected in parallel to each other.

20. The tunable capacitor array of claim 18, wherein an equivalent capacitance of the plurality of the tunable capacitors is 2^m-1×

C1 (here, m is a natural number less than or equal to n), wherein channel width-to-length ratios W/L of the switching transistors of the plurality of the tunable capacitors are 2^m-1×

W1 (here, m is a natural number less than or equal to n) respectively, and wherein the n is a number of the tunable capacitors, wherein the C1 is an equivalent capacitance of a particular tunable capacitor, and wherein the W1 is a channel width-to-length ratio W/L of the switching transistor.

21. The tunable capacitor array of claim 18, further comprising a fixed capacitor which is connected in parallel to a plurality of the tunable capacitors.

22. The tunable capacitor array of claim 20, further comprising a fixed capacitor which is connected in parallel to a plurality of the tunable capacitors.

23. The tunable capacitor array of claim 18, further comprising a controller which receives a digital control signal and controls on/off of the switching transistor.

24. The tunable capacitor array of claim 20, further comprising a controller which receives a digital control signal and controls on/off of the switching transistor.