Storage method and apparatus for random access memory using codeword storage

• US 9,524,106 B1
• Filed: 06/07/2016
• Issued: 12/20/2016
• Est. Priority Date: 05/14/2012
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Cronie, Harm, Shokrollahi, Amin
• Primary Examiner(s): Tu, Christine
• Application Number:
  US15/176,081
• Time in Patent Office: 196 Days
• Field of Search: 714/763, 714/773, 714/778, 714/758
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1505 Golay Codes
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes

Abstract

A memory circuit, such as an embedded DRAM array, stores information as groups of bits or data using information coding in storage and retrieval data, instead of each bit being stored separately. Write data words can be mapped to storage format words that are stored and defined by a Hadamard matrix. The storage format word is stored as charge levels in an addressable memory location. For retrieving stored data, charge levels are read from the storage cells and interpreted to a valid storage format word. Hadamard code maximal likelihood decoding can be used to derive a read data word corresponding to a previously written write data word. The write data word is then output as the result of a read of the selected addressable location, or a portion thereof. The mapping can be two or more Hadamard matrix mappings concatenated for each of a plurality of storage format words.

Claims

1. A method comprising:

receiving a set of B input bits, wherein B is an integer greater than 2;

selecting at least a first and a second state value according to the set of B input bits, each state value selected from a respective set of N−

1 possible state values, N being a power of 2, wherein 2*(log₂(N)−

1)<

B, and wherein a total number of state value combinations is greater than 2^B;

generating at least two storage format words by applying, for each of the selected state values, a respective numerical vector to a Hadamard matrix of size N, wherein each storage format word is generated by subtracting at least one respective Walsh function from a weighted all-one Walsh function, the all-one Walsh function corresponding to an all-one row of a Hadamard matrix, each respective Walsh function corresponding to rows of the Hadamard matrix orthogonal to the all-one row, the at least one respective Walsh function determined by the respective numerical vector;

selecting a subset of storage cells from a plurality of storage cells according to an address input; and

storing the at least two storage format words in the selected subset of storage cells.

2. The method of claim 1, wherein the weighted all-one Walsh function has a weight of n, and wherein n Walsh functions are subtracted from the weighted all-one Walsh function, wherein n is an integer greater than or equal to 1, and less than the size N of the Hadamard matrix.

3. The method of claim 1, wherein determining the at least first and second state values comprises performing Boolean logic on the received set of B input bits.

4. The method of claim 1, wherein B is equal to 5, and wherein each of the at least first and second state values are selected from a respective set of N−

1=7 possible state values.

5. The method of claim 1, wherein B is equal to 8, and wherein the at least first and second state values comprises a third state value, each of the first, second, and third state values selected from a respective set of N−

1=7 possible state values.

6. The method of claim 1, wherein B is equal to 19, and wherein the at least first and second state values comprises a third, a fourth and a fifth state value, each of the first, second, third, fourth and fifth state values selected from a respective set of N−

1=15 possible state values.

7. The method of claim 1, wherein at least one state value is determined using a lookup table.

8. The method of claim 1, further comprising:

reading a plurality of voltage readouts from a plurality of read storage cells; and

decoding the plurality of voltage readouts into a plurality of read state values.

9. The method of claim 8, further comprising applying an inverse lookup table to the plurality of read state values to obtain a plurality of output bits.

10. The method of claim 8, further comprising applying Boolean logic to the read state values to obtain a plurality of output bits.

11. An apparatus comprising:

an encoder configured to;

receive a set of B input bits, and to select at least a first and a second state value according to the set of B input bits, each state value selected from a respective set of N−

1 possible state values, N being a power of 2, wherein 2*(log₂(N)−

1)<

B, and wherein a total number of state value combinations is greater than 2^B; and

generate a at least two storage format words by applying, for each of the selected state values, a respective numerical vector to a Hadamard matrix of size N, wherein each storage format word is generated by subtracting at least one respective Walsh function from a weighted all-one Walsh function, the all-one Walsh function corresponding to an all-one row of a Hadamard matrix, each respective Walsh function corresponding to rows of the Hadamard matrix orthogonal to the all-one row, the at least one respective Walsh function determined by the respective numerical vector; and

a memory write circuit configured to select a subset of storage cells from a plurality of storage cells according to an address input, and to store the at least two storage format words in the selected subset of storage cells.

12. The apparatus of claim 11, wherein the weighted all-one Walsh function has a weight of n, and wherein n Walsh functions are subtracted from the weighted all-one Walsh function, wherein n is an integer greater than or equal to 1, and less than the size N of the Hadamard matrix.

13. The apparatus of claim 11, wherein the encoder is a logic encoder configured to determine the at least first and second state values by performing Boolean logic on the received set of B input bits.

14. The apparatus of claim 11, wherein B is equal to 5, and wherein, each of the first and second state values are selected from a respective set of N−

1=7 possible state values.

15. The apparatus of claim 11, wherein B is equal to 8, and wherein the at least first and second state values comprises a third state value, each of the first, second, and third state values selected from a respective set of N−

1=7 possible state values.

16. The apparatus of claim 11, wherein B is equal to 19, and wherein the at least first and second state values comprises a third, fourth, and fifth state value each of the first, second, third, fourth, and fifth state values selected from a respective set of N−

1=15 possible state values.

17. The apparatus of claim 11, wherein the encoder is configured to determine at least one state value using a lookup table.

18. The apparatus of claim 11, further comprising:

a memory read circuit configured to read a plurality of voltage readouts from a plurality of read storage cells; and

a decoder configured to decode the plurality of voltage readouts into a plurality of read state values.

19. The apparatus of claim 18, wherein the decoder is configured to apply an inverse lookup table to the plurality of read state values to obtain a plurality of output bits.

20. The apparatus of claim 18, wherein the decoder is configured to apply Boolean logic to the read state values to obtain a plurality of output bits.