Computer processor employing hardware-based pointer processing
First Claim
1. A computer processor comprising:
- at least one mask register that includes a number of interest bits whose values represent whether a possible event would be of interest if it did occur; and
execution logic that performs operations that utilize pointers stored in a memory system operably coupled to the computer processor;
wherein each pointer stores a value representing a memory address and is associated with a predefined number of event bits separate from the memory address value of the pointer;
wherein the execution logic is configured to process the interest bits stored in the at least one mask register and the event bits associated with a given pointer in conjunction with the processing of a predefined memory-related operation that involves the given pointer in order to selectively output an event-of-interest signal that provides an indication that an event-of-interest has occurred;
wherein the at least one mask register corresponds to at least one predefined class of memory-related operations;
wherein the event bits of the given pointer are used to generate an index into the mask register; and
wherein the index is used to access and select a corresponding interest bit of the mask register and then process the selected interest bit in order to selectively output the event-of-interest signal based upon the value of the selected interest bit.
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Abstract
A computer processor is provided with execution logic that performs operations that utilize pointers stored in memory. In one aspect, each pointer is associated with a predefined number of event bits. The execution logic processes the event bits of a given pointer in conjunction with processing a predefined pointer-related operation involving the given pointer in order to selectively output an event-of-interest signal.
In another aspect, each pointer is represented by an address field and a granularity field. The address field includes a chunk address and an offset. The granularity field represents granularity of the offset of the address field. The execution logic includes an address derivation unit that processes the granularity field of a base address for a given pointer in order to generate a valid address field for the derived pointer.
15 Citations
23 Claims
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1. A computer processor comprising:
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at least one mask register that includes a number of interest bits whose values represent whether a possible event would be of interest if it did occur; and execution logic that performs operations that utilize pointers stored in a memory system operably coupled to the computer processor; wherein each pointer stores a value representing a memory address and is associated with a predefined number of event bits separate from the memory address value of the pointer; wherein the execution logic is configured to process the interest bits stored in the at least one mask register and the event bits associated with a given pointer in conjunction with the processing of a predefined memory-related operation that involves the given pointer in order to selectively output an event-of-interest signal that provides an indication that an event-of-interest has occurred; wherein the at least one mask register corresponds to at least one predefined class of memory-related operations; wherein the event bits of the given pointer are used to generate an index into the mask register; and wherein the index is used to access and select a corresponding interest bit of the mask register and then process the selected interest bit in order to selectively output the event-of-interest signal based upon the value of the selected interest bit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A computer processor comprising:
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execution logic that performs operations that utilize pointers stored in a memory system operably coupled to the computer processor; wherein each pointer is represented by an address field and a granularity field, wherein address field includes a chunk address and an offset, and wherein the granularity field represents the granularity of the offset of the address field; wherein the execution logic includes an address derivation unit that processes the granularity field for a given pointer in order to determine granularity of the offset of the address field for the given pointer, wherein the address derivation unit is configured to processes the granularity field of a base address of a pointer to determine the offset of the base address for the pointer and calculates a pointer effective address based on the base address of the pointer, the address derivation unit is further configured to check for an offset part overflow condition in calculating the pointer effective address, wherein the offset part overflow condition occurs when the address field of the effective address differs from the address field of a base address beyond the offset part of the pointer effective address, and the address derivation unit outputs a valid pointer effective address in the event that the offset part overflow condition is not detected. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
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Specification