Atomic transactions to non-volatile memory

• US 9,524,219 B2
• Filed: 09/27/2013
• Issued: 12/20/2016
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bahnsen, Robert, Sakthivelu, Sridharan, Saletore, Vikram A., Viswanathan, Krishnaswamy, Tolentino, Matthew E., Govindaraju, Kanivenahalli, Zimmer, Vincent J.
• Primary Examiner(s): Chace, Christian P
• Assistant Examiner(s): LOONAN, ERIC T
• Application Number:
  US14/040,380
• Publication Number:
  US 20150095600A1
• Time in Patent Office: 1,180 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1474 in transactions G06F16/20 takes precedence
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 9/466 Transaction processing

Abstract

Durable atomic transactions for non-volatile media are described. A processor includes an interface to a non-volatile storage medium and a functional unit to perform instructions associated with an atomic transaction. The instructions are to update data at a set of addresses in the non-volatile storage medium atomically. The functional unit is operable to perform a first instruction to create the atomic transaction that declares a size of the data to be updated atomically. The functional unit is also operable to perform a second instruction to start execution of the atomic transaction. The functional unit is further operable to perform a third instruction to commit the atomic transaction to the set of addresses in the non-volatile storage medium, wherein the updated data is not visible to other functional units of the processing device until the atomic transaction is complete.

Claims

1. A processing device comprising:

a cache;

an interface to a non-volatile storage medium (NVM) operatively coupled to the cache; and

a first functional unit to execute a plurality of instructions associated with an atomic transaction and to track execution of the atomic transaction with a first transaction identifier (TID), wherein the plurality of instructions are to replace data at a set of addresses in the NVM atomically with new data, wherein the first functional unit is to execute the plurality of instructions to;

perform a first instruction to create the atomic transaction that delineates a size of the data to be replaced atomically and generates the first TID;

perform a second instruction to execute the atomic transaction including storing, in first cache lines of the cache, the new data with the set of addresses and the first TID;

perform a third instruction to commit the atomic transaction to the set of addresses in the NVM, wherein the new data is not visible to other functional units until the atomic transaction is complete; and

wherein the second instruction and the third instruction are further to, in response to a read request from a second functional unit to an address of the set of addresses;

determine that the read request lacks the first TID;

access the data associated with the address in a second cache line of the cache that is not associated with a valid TID in response to determining that the read request lacks the first TID, wherein the new data is simultaneously available in the first cache lines when accessing the data in the second cache line; and

send, to the second functional unit, the data for the address.

2. The processing device of claim 1, wherein during performance of the first instruction, the first functional unit is further to change a state of the set of addresses to an invalid state after creating the atomic transaction.

3. The processing device of claim 2, wherein before performance of the second instruction, the first functional unit is further to perform a fourth instruction to register the set of addresses to be modified during the atomic transaction in a transaction tracker.

4. The processing device of claim 2, wherein before performance of the second instruction, the first functional unit is further to:

change the state of the set of addresses to a locked state, and

change the state of the set of addresses from the locked state to a processing state when the state of each of the set of addresses are in the locked state, to start execution of the atomic transaction.

5. The processing device of claim 1, wherein during performance of the third instruction, the first functional unit is further to write the new data for the set of addresses to an intermediate memory location before committing the new data for the set of addresses to the NVM, and

wherein the first functional unit is to lock the set of addresses after writing the new data for the set of addresses to the intermediate memory location and before committing the new data for the set of addresses to the NVM.

6. The processing device of claim 5, wherein after performance of the third instruction, the first functional unit is further to change a state of the set of addresses to a visible state to unlock the set of addresses after the atomic transaction has been committed to the set of addresses in the NVM.

7. The processing device of claim 5, wherein the intermediate memory location is a memory element in the cache, wherein during performance of the third instruction, the first functional unit is further to:

write the new data from the cache to a buffer of the NVM while the set of addresses are in a locked state; and

unlock the set of addresses when the new data is written from the cache to the buffer of the NVM.

8. The processing device of claim 1, wherein, before execution of the first instruction, the first functional unit is further to store in second cache lines, including the second cache line, of the cache the data for the set of addresses, each associated with a TID value of zero, indicating the set of addresses is not associated with a valid transaction.

9. The processing device of claim 8, wherein the second functional unit is to execute a thread, wherein the data is returned to the second functional unit from the cache when the thread requests to access any address of the set of addresses associated with the atomic transaction.

10. The processing device of claim 1, wherein the third instruction is further to, in response to a read request to the address from the first functional unit, send to the first functional unit the new data for the address stored in the first cache lines after determining that the read request includes the first TID.

11. The processing device of claim 1, wherein writing the new data for the set of addresses to the NVM according to the third instruction comprises writing the new data to a buffer of the NVM from the cache.

12. The processing device of claim 11, wherein the first functional unit is further to write the new data from the buffer of the non-volatile storage medium to the set of addresses of the NVM.

13. The processing device of claim 1, wherein the first functional unit is further to invalidate the first TID after the atomic transaction has been committed.

14. The processing device of claim 1, wherein the NVM is byte-addressable persistent memory.

15. A method comprising:

creating, by a first functional unit of a processing device, an atomic transaction that delineates a size of a set of addresses to be written atomically and tracks execution of the atomic transaction with a first transaction identifier (TID), wherein execution of the atomic transaction directs the processing device to replace data at the set of addresses in a non-volatile storage medium (NVM) with new data from the atomic transaction;

executing, by the first functional unit, the atomic transaction including storing the new data in first cache lines of a cache with the set of addresses and the first TID;

committing, by the first functional unit, the atomic transaction to the set of addresses in the NVM, wherein the new data is not visible to other functional units of the processing device until the atomic transaction is complete;

wherein, during the executing and the committing the atomic transaction, and in response to a read request from a second functional unit to an address of the set of addresses;

determine that the read request lacks the first TID;

access the data associated with the address in a second cache line of the cache that is not associated with a valid TID in response to determining that the read request lacks the first TID, wherein the new data is simultaneously available in the first cache lines when accessing the data in the second cache line; and

sending, to the second functional unit, the data for the address.

16. The method of claim 15, further comprising unlocking the set of addresses after committing the atomic transaction to the set of addresses in the NVM.

17. The method of claim 16, wherein writing to the set of addresses comprises replacing the data with the new data, the method further comprising, before the set of addresses is unlocked, providing, by the processing device, the data to the second functional unit that is not associated with the atomic transaction.

18. The method of claim 15, further comprising registering the atomic transaction to indicate that the set of addresses is to be modified during execution of the atomic transaction.

19. The method of claim 15, further comprising:

writing the new data associated with the set of addresses in an intermediate memory location before committing the atomic transaction to the set of addresses in the NVM, and

wherein committing the atomic transaction to the set of addresses in the NVM comprises writing the new data associated with the set of addresses from the intermediate memory location to the NVM.

20. The method of claim 19, wherein the intermediate memory location is a memory element in a buffer of the NVM.

21. The method of claim 19, wherein the intermediate memory location is a memory element in the cache, the method further comprising:

writing the new data from the cache to a memory element in a buffer of the NVM while the set of addresses are locked; and

unlocking the set of addresses when the new data is written from the cache to the buffer of the NVM.

22. The method of claim 15, further comprising

sending, to the first functional unit in response to a read request to the address from the first functional unit, the new data for the address stored in the first cache lines after determining that the read request includes the first TID.

23. The method of claim 15, wherein the data is received by the second functional unit from the cache.

24. A non-transitory machine-readable storage medium including instructions that, when executed by a processor, cause the processor to:

create, by a first functional unit of the processor, an atomic transaction that delineates a size of data to be replaced atomically and tracks execution of the atomic transaction with a first transaction identifier (TID), wherein execution of the atomic transaction comprises replacing the data at a set of addresses in a non-volatile storage medium (NVM) with new data from the atomic transaction, wherein the NVM is byte-addressable persistent memory;

execute, by the first functional unit, the atomic transaction to include storing the new data in first cache lines of a cache with the set of addresses and the first TID; and

commit, by the first functional unit, the atomic transaction to the set of addresses in the NVM, wherein the new data is not visible to other functional units of the processor until the atomic transaction is complete;

wherein, before completion of the atomic transaction and in response to a read request from a second functional unit to an address of the set of addresses, the instructions further to cause the processor to;

determine that the read request lacks the first TID;

access the data associated with the address in a second cache line of the cache that is not associated with a valid TID in response to determining that the read request lacks the first TID, wherein the new data is simultaneously available in the first cache lines when accessing the data in the second cache line; and

send, to the second functional unit, the data for the address.

25. The non-transitory machine-readable storage medium of claim 24, wherein the instructions further to, when executed by the processor, cause the processor to, in response to a read request to the address from the first functional unit, send to the first functional unit the new data for the address stored in the first cache lines after determining that the read request includes the first TID.