Method and apparatus for bus lock assistance
First Claim
Patent Images
1. A method comprising:
- detecting that a first instruction and a second instruction are locked instructions;
determining that execution of the first instruction and the second instruction each include imposing a bus lock; and
executing a bus lock assistance function in response to said determining, wherein the bus lock assistance function comprises;
preventing the bus lock from being imposed for the first instruction, andpermitting the bus lock to be imposed for the second instruction and causing a save of state information of an instruction execution pipeline that executes the second instruction.
1 Assignment
0 Petitions
Accused Products
Abstract
A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.
-
Citations
23 Claims
-
1. A method comprising:
-
detecting that a first instruction and a second instruction are locked instructions; determining that execution of the first instruction and the second instruction each include imposing a bus lock; and executing a bus lock assistance function in response to said determining, wherein the bus lock assistance function comprises; preventing the bus lock from being imposed for the first instruction, and permitting the bus lock to be imposed for the second instruction and causing a save of state information of an instruction execution pipeline that executes the second instruction. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. An apparatus comprising:
-
instruction identification logic circuitry to identify when a first instruction and a second instruction are locked instructions; first logic circuitry to determine if the first instruction and the second instruction are each to impose a bus lock when executed; and second logic circuitry to trigger a bus lock assistance function when the first instruction and the second instruction are to each impose the bus lock when executed, wherein the bus lock assistance function is to; prevent the bus lock from being imposed for the first instruction, and permit the bus lock to be imposed for the second instruction and cause a save of state information of an instruction execution pipeline that executes the second instruction. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
-
-
17. A non-transitory machine readable medium containing program instructions that when processed by a processing core causes a method to be performed, said method comprising:
-
detecting that a first instruction of a thread and a second instruction are locked instructions; determining that execution of the first instruction and the second instruction includes imposing a bus lock; and executing a bus lock assistance function in response to said determining, wherein the bus lock assistance function comprises; preventing the bus lock from being imposed for the first instruction, and permitting the bus lock to be imposed for the second instruction and causing a save of state information of an instruction execution pipeline that executes the second instruction. - View Dependent Claims (18, 19, 20, 21, 22, 23)
-
Specification