Modular array of vertically integrated superconducting qubit devices for scalable quantum computing

• US 9,524,470 B1
• Filed: 06/12/2015
• Issued: 12/20/2016
• Est. Priority Date: 06/12/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chow, Jerry M., Gambetta, Jay M., Rothwell, Mary B., Rozen, James R.
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US14/737,707
• Publication Number:
  US 20160364653A1
• Time in Patent Office: 557 Days
• Field of Search: 438/2, 257/31, 257/36
• US Class Current: 1/1
• CPC Class Codes: G06N 10/00 Quantum computing, i.e. information processing based on quantum-mechanical phenomena
• CPC Class Codes: H01L 25/04 the devices not having separate containers
• CPC Class Codes: H10N 60/0912 of Josephson-effect devices
• CPC Class Codes: H10N 60/12 Josephson-effect devices
• CPC Class Codes: H10N 60/815 for Josephson-effect devices
• CPC Class Codes: H10N 69/00 Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00

Abstract

A technique relates to an assembly for a quantum computing device. A quantum bus plane includes a first set of recesses. A readout plane includes a second set of recesses. A block is positioned to hold the readout plane opposite the quantum bus plane, such that the first set of recesses opposes the second set of recesses. A plurality of qubit chips are included where each has a first end positioned in the first set of recesses and has a second end positioned in the second set of recesses.

Claims

1. A method of configuring an assembly for a quantum computing device, the method comprising:

providing a quantum bus plane having a first set of recesses and a readout plane having a second set of recesses;

positioning the readout plane opposite the quantum bus plane in a block, such that the first set of recesses opposes the second set of recesses; and

installing a plurality of qubit chips in the block, each of the plurality of qubit chips having a first end positioned in the first set of recesses and having a second end positioned in the second set of recesses.

2. The method of claim 1, wherein the plurality of qubit chips extend vertically in a lengthwise direction by being positioned in both the first set of recesses and the second set of recesses.

3. The method of claim 1, wherein the first set of recesses holds the first end of the plurality of qubit chips in the readout plane;

and

wherein the second set of recesses holds the second end of the plurality of qubit chips in the quantum bus plane; and

wherein the first end of the plurality of qubit chips is opposite the second end.

4. The method of claim 1, wherein the quantum bus plane comprises a substrate with interconnect wiring on top of the substrate, the interconnect wiring connecting the plurality of qubit chips via a plurality of coupling bus resonators.

5. The method of claim 1, wherein the readout plane comprises a substrate with fan-out wiring on top of the substrate, the fan-out wiring individually connecting each of the plurality of qubit chips to a circuit board;

and

wherein the circuit board individually connects each of the plurality of qubit chips to a plurality of connectors in a one-to-one relationship.

6. The method of claim 1, wherein the block is configured to receive a first assembly comb and a second assembly comb to form an intersection, the intersection of the first and second assembly combs forming a plurality of slots for individually accepting the plurality of qubit chips;

and

wherein the plurality of slots mechanically hold the plurality of qubit chips in a vertical position.

7. A method of configuring an assembly for a quantum computing device, the method comprising:

providing a housing configured as an enclosure having a bottom part, a top part, and a block, the block connecting the top and bottom parts;

providing a readout plane having a first set of recesses and a quantum bus plane having a second set of recesses;

assembling the readout plane opposite the quantum bus plane in a block, such that the first set of recesses opposes the second set of recesses; and

installing a plurality of qubit chips in the block, each of the plurality of qubit chips having a first end positioned in the first set of recesses and having a second end positioned in the second set of recesses.

8. The method of claim 7, wherein the housing includes a readout plane housing slot through which the readout plane extends;

and

wherein the readout plane extends through the readout plane housing slot to connect to a circuit board, the circuit board connecting to a plurality of connectors.

9. The method of claim 7, wherein the housing includes a pushing mechanism configured to apply pressure to the readout plane, the pressure applied to the readout plane forces the plurality of qubit chips to the quantum bus plane.

10. The method of claim 9, wherein the pushing mechanism comprises:

a pusher block positioned on top of the readout plane, and

a spring mechanism pressing downward against the pusher block, the top part of the housing applying a compression force to the spring mechanism from above.