Methods and systems on chip for updating frames based on an indication signal for a display system

• US 9,524,533 B2
• Filed: 03/04/2014
• Issued: 12/20/2016
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jong Hyup, Kim, Kyoung Man
• Primary Examiner(s): Crawford, Jacinta M
• Assistant Examiner(s): Cofino, Jonathan M
• Application Number:
  US14/196,120
• Publication Number:
  US 20140267329A1
• Time in Patent Office: 1,022 Days
• US Class Current: 1/1
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G09G 2310/04 Partial updating of the display screen
• CPC Class Codes: G09G 2330/022 in absence of operation, e.g. no data being entered during a predetermined time
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

A method of operating a display system may include receiving an indication signal indicating a data update, receiving data, and updating a whole frame on the display with an image corresponding to the data based on the indication signal corresponding to a whole frame or updating a partial frame on the display with an image corresponding to the data based on the indication signal corresponding to a partial frame.

Claims

1. An operation method of a display system comprising:

detecting a first update region where a display image is to be updated;

determining a first determination to update a partial frame included in a whole frame on a display based on the first update region being completely contained within a predefined partial frame region, wherein the predefined partial frame region is less than a whole frame region;

receiving a first indication signal indicating a first data update and corresponding to the first determination to update the partial frame included in the whole frame;

receiving first data;

updating the partial frame on the display with an image corresponding to the first data based on the first indication signal corresponding to the first determination to update the partial frame;

detecting a second update region where the display image is to be updated;

determining a second determination to update the whole frame based on at least a portion of the second update region being outside of the predefined partial frame region;

receiving a second indication signal indicating a second data update and corresponding to the second determination to update the whole frame;

receiving second data; and

updating the whole frame on the display with an image corresponding to the second data based on the second indication signal corresponding to the second determination to update the whole frame.

2. The operation method of claim 1, wherein the first and second indication signals are included in header portions of data packets that also include the respective data.

3. The operation method of claim 1, wherein the first and second indication signals are transmitted in back porch intervals of respective first and second vertical synchronization signals.

4. The operation method of claim 3, wherein the first data is transmitted in a first time portion between the back porch interval and a front porch interval of the first vertical synchronization signal and wherein data is not transmitted in a second time portion between the back porch interval and the front porch interval of the first vertical synchronization signal.

5. The operation method of claim 1, wherein the first and second indication signals and the first and second data are suitable for an RGB interface.

6. A system on chip (SoC) comprising:

an update detecting circuit configured to generate a first update control signal corresponding to a first determination to update a partial frame included in a whole frame based on a first update region being completely contained within a predefined partial frame region and configured to generate a second update control signal corresponding to a second determination to update the whole frame based on at least a portion of a second update region being outside of the predefined partial frame region; and

an update control circuit configured to generate a first indication signal corresponding to the first update control signal and configured to generate a second indication signal corresponding to the second update control signal.

7. The system on chip (SoC) of claim 6, wherein the update control circuit comprises:

a special function register configured to set a plurality of addresses defining the partial frame; and

a control circuit configured to generate the first indication signal corresponding to the first update control signal and the plurality of addresses defining the partial frame.

8. The system on chip (SoC) of claim 7, wherein the update control circuit further includes an encoder configured to encode the first and second indication signals.

9. The system on chip (SoC) of claim 6, wherein the first and second indication signals are included in header portions of data packets.

10. The system on chip (SoC) of claim 6, further comprising:

an encoder configured to generate first and second encoded indication signals by encoding the first and second indication signals, respectively; and

a transmission interface configured to transmit the encoded first and second indication signals during back porch intervals of respective first and second vertical synchronization signals.

11. The system on chip (SoC) of claim 10, further comprising a dynamic memory access (DMA) controller configured to read data corresponding to only the partial frame based on the first determination to update the partial frame,

wherein the transmission interface is further configured to transmit the data in a first time portion between the back porch interval and a front porch interval of the first vertical synchronization signal and wherein data is not transmitted in a second time portion between the back porch interval and the front porch interval of the first vertical synchronization signal.

12. The system on chip (SoC) of claim 10, wherein the transmission interface is an RGB interface.

13. An operation method of a display system comprising:

detecting a first update region where a display image is to be updated;

determining a first determination to update a partial frame included in a whole frame based on the first update region being completely contained within a predefined partial frame region, wherein the predefined partial frame region is less than a whole frame region;

transmitting a first display data relating only to the predefined partial frame region based upon the first determination to update the partial frame;

updating a display image corresponding to the first display data;

detecting a second update region where a display image is to be updated;

determining a second determination to update the whole frame based on at least a portion of the second update region being outside the predefined partial frame region;

transmitting a second display data relating to the whole frame region based upon the second determination to update the whole frame; and

updating the display image corresponding to the second display data.

14. The operation method of claim 13, further comprising transmitting a first indication signal which indicates the predefined partial frame region corresponding to the first display data.

15. The operation method of claim 14, further comprising:

receiving the first display data and first indication signal at a display driver; and

updating a video memory within the display driver based upon the first display data and first indication signal.

16. The operation method of claim 13, wherein the display image corresponding to a region including all of the whole frame region outside of the predefined partial frame region remains unchanged when updating the display image corresponding to the first display data relating only to the predefined partial frame region.