Memory device of a single-ended bitline structure including reference voltage generator

• US 9,524,772 B2
• Filed: 07/07/2015
• Issued: 12/20/2016
• Est. Priority Date: 08/11/2014
• Status: Active Grant

• Current Assignee: Korea University Research and Business Foundation, Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Rim, Woojin, Song, Taejoong, Kim, Gyuhong, Park, Jongsun, Choi, Woong
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US14/793,053
• Publication Number:
  US 20160042785A1
• Time in Patent Office: 532 Days
• Field of Search: 365/154, 365/156, 365/185.2, 365/189.07, 365/189.09, 365/205, 365/207, 365/208, 365/210.1, 365/230.03, 365/63, 365/230.05
• US Class Current: 1/1
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A memory device includes a first memory cell array including memory cells of a single-ended bitline structure, a second memory cell array including memory cells of a single-ended bitline structure, a reference voltage generator configured to output a bitline voltage of a selected one of the first and second memory cell arrays as a sensing voltage according to an array select signal and output a bitline voltage of an unselected memory cell array as a reference voltage, and a differential sense amplifier configured to amplify and output a difference between the sensing voltage and the reference voltage. Logic states of the sensing voltage and the reference voltage are complementary to each other.

Claims

1. A memory device comprising:

a first memory cell array comprising memory cells of a single-ended bitline structure;

a second memory cell array comprising memory cells of a single-ended bitline structure;

a reference voltage generator configured to receive a bitline voltage from the first memory cell array and a bitline voltage from the second memory cell array, configured to select one of the first memory cell array and the second memory cell array and configured to output the bitline voltage of the selected one of the first and second memory cell arrays as a sensing voltage according to an array select signal and to output the bitline voltage of an unselected memory cell array as a reference voltage; and

a differential sense amplifier configured to receive the sensing voltage and the reference voltage and configured to amplify and output a difference between the sensing voltage and the reference voltage,

wherein logic states of the sensing voltage and the reference voltage are complementary to each other.

2. The memory device of claim 1, wherein the reference voltage generator adjusts a level of the bitline voltage of the unselected memory cell according to a level of the bitline voltage of the selected memory cell array and outputs the adjusted bitline voltage as the reference voltage.

3. The memory device of claim 2, wherein the array select signal includes a first select signal indicating whether the first memory cell array is selected and a second select signal indicating whether the second memory cell array is selected, and wherein logic states of the first and second select signals are complementary to each other.

4. The memory device of claim 3, wherein the reference voltage generator comprises:

a first voltage output unit configured to receive the bitline voltage of the first memory cell and the first select signal and configured to output the bitline voltage of the first memory cell array as the sensing voltage or the reference voltage according to the first select signal and the bitline voltage of the second memory cell array; and

a second voltage output unit configured to receive the bitline voltage of the second memory cell and the second select signal and configured to output the bitline voltage of the second memory cell array as the sensing voltage or the reference voltage according to the second select signal and the bitline voltage of the first memory cell array.

5. The memory device of claim 4, wherein the first voltage output unit outputs the bitline voltage of the first memory cell array as the sensing voltage and the second voltage output unit outputs the bitline voltage of the second memory cell array as the reference voltage when the first select signal is logic high.

6. The memory device of claim 5, wherein the first voltage output unit outputs the bitline voltage of the first memory cell array as the reference voltage and the second voltage output unit outputs the bitline voltage of the second memory cell array as the sensing voltage when the second select signal is logic high.

7. The memory device of claim 4, wherein the first voltage output unit includes a first pull-down transistor and a second pull-down transistor that are connected in series and configured to drive the bitline voltage of the first memory cell array to a ground voltage level in response to the first select signal and the bitline voltage of the second memory cell array.

8. The memory device of claim 7, wherein the second voltage output unit includes a third pull-down transistor and a fourth pull-down transistor that are connected in series and configured to drive the bitline voltage of the second memory cell array to a ground voltage level in response to the second select signal and the bitline voltage of the first memory cell array.

9. The memory device of claim 8, further comprising:

a multiplexer configured to output a data signal corresponding to a logic state of data stored in the selected memory cell in response to an output signal of the differential sense amplifier and the first and second select signals.

10. A memory device of an open bitline structure, comprising:

an upper memory cell array comprising memory cells of a single-ended bitline structure;

a lower memory cell array comprising memory cells of a single-ended bitline structure;

an address decoder configured to output an array select signal selecting one of the upper and lower memory cell arrays in response to an address signal;

a reference voltage generator configured to receive a bitline voltage from the upper memory cell array and a bitline voltage from the lower memory cell array, configured to select one of the upper memory cell array and the lower memory cell array and configured to output the bitline voltage of the selected memory cell array as a sensing voltage and to output the bitline voltage of an unselected memory cell array as a reference voltage according to the array select signal; and

a differential sense amplifier configured to receive the sensing voltage and the reference voltage and configured to amplify and output a difference between the sensing voltage and the reference voltage,

wherein logic states of the sensing voltage and the reference voltage are complementary to each other.

11. The memory device of claim 10, wherein the reference voltage generator adjusts a level of the bitline voltage of the unselected memory cell according to a level of the bitline voltage of the selected memory cell array and outputs the adjusted bitline voltage as the reference voltage.

12. The memory device of claim 11, wherein the address decoder outputs an upper select signal indicating whether the upper memory cell array is selected and a lower select signal indicating whether the lower memory cell array is selected, and wherein logic states of the upper and lower select signals are complementary to each other.

13. The memory device of claim 12, wherein the reference voltage generator comprises:

a first voltage output unit configured to receive the bitline voltage of the upper memory cell and the upper select signal and configured to output the bitline voltage of the upper memory cell array as the sensing voltage or the reference voltage according to the upper select signal and the bitline voltage of the lower memory cell array; and

a second voltage output unit configured to receive the bitline voltage of the lower memory cell and the lower select signal and configured to output the bitline voltage of the lower memory cell array as the sensing voltage or the reference voltage according to the lower select signal and the bitline voltage of the upper memory cell array.

14. The memory device of claim 13, wherein the first voltage output unit outputs the bitline voltage of the upper memory cell array as the sensing voltage when the upper select signal is logic high and outputs a logic-high or logic-low reference voltage according to a level of the bitline voltage of the lower memory cell array when the upper select signal is logic low.

15. The memory device of claim 14, wherein the second voltage output unit outputs the bitline voltage of the lower memory cell array as the sensing voltage when the lower select signal is logic high and outputs a logic-high or logic-low reference voltage according to a level of the bitline voltage of the upper memory cell array when the lower select signal is logic low.

16. A memory device comprising:

a first memory cell array comprising memory cells of a single-ended bitline structure and configured to output a first bitline voltage;

a second memory cell array comprising memory cells of a single-ended bitline structure and configured to output a second bitline voltage;

a reference voltage generator configured to receive the first bitline voltage from the first memory cell array and the second bitline voltage from the second memory cell array, configured to select one of the first bitline voltage and the second bitline voltage and configured to output a selected one of the first and second bitline voltages as a sensing voltage according to an array select signal and to output an unselected one of the first and second bitline voltages as a reference voltage after adjusting the bitline voltage of an other of the first and second bitline voltages according to the selected one of the first and second bitline voltages; and

a differential sense amplifier configured to receive the sensing voltage and the reference voltage and configured to amplify and output a difference between the sensing voltage and the reference voltage.

17. The memory device of claim 16, wherein logic states of the sensing voltage and the reference voltage are complementary to each other.

18. The memory device of claim 17, wherein the array select signal includes a first select signal indicating whether the first memory cell array is selected and a second select signal indicating whether the second memory cell array is selected, and wherein logic states of the first and second select signals are complementary to each other.

19. The memory device of claim 18, wherein the reference voltage generator comprises:

a first voltage output unit configured to receive the first bitline voltage and the first select signal and configured to output the first bitline voltage as the sensing voltage or the reference voltage according to the first select signal and the second bitline voltage; and

a second voltage output unit configured to receive the second bitline voltage and the second selected signal and configured to output the second bitline voltage as the sensing voltage or the reference voltage according to the second select signal and the first bitline voltage.

20. The memory device of claim 19, wherein the first voltage output unit outputs the first bitline voltage as a sensing voltage when the first select signal is logic high and outputs a logic-high or logic-low reference voltage according to a level of the second bitline voltage when the first select signal is logic low, and wherein the second voltage output unit outputs the second bitline voltage as the sensing voltage when the second select signal is logic high and outputs a logic-high or logic-low reference voltage according to a level of the first bitline voltage when the lower select signal is logic low.