Correlation detector
First Claim
1. A correlation detector comprising:
- an input unit configured to receive a plurality of parallel data streams of discrete events;
a memory array comprising a plurality of resistive memory elements, wherein at least one of the resistive memory elements is allocated to each of the data streams;
a programming array comprising a plurality of programming elements, wherein at least one of the programming elements is allocated to each resistive memory element for applying a programming signal to the respective memory element;
a control unit configured to control the programming signals as a function of a co-arrival characteristic of the discrete events;
a correlation unit configured to detect correlations between the data streams based on resistance changes of the resistive memory elements.
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Abstract
A correlation detector comprises an input unit configured to receive a plurality of parallel data streams of discrete events. The correlation detector further comprises a memory array having a plurality of resistive memory elements. At least one resistive memory element is allocated to each of the parallel data streams. Furthermore, a programming array is provided comprising a plurality of programming elements. At least one programming element is allocated to each resistive memory element for applying a programming signal to the respective memory element. The correlation detector comprises further a control unit that is configured to control the programming signals as a function of a co-arrival characteristic of the discrete events. A correlation unit is configured to detect correlations between the received data streams based on resistance changes of the resistive memory elements.
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Citations
12 Claims
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1. A correlation detector comprising:
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an input unit configured to receive a plurality of parallel data streams of discrete events; a memory array comprising a plurality of resistive memory elements, wherein at least one of the resistive memory elements is allocated to each of the data streams; a programming array comprising a plurality of programming elements, wherein at least one of the programming elements is allocated to each resistive memory element for applying a programming signal to the respective memory element; a control unit configured to control the programming signals as a function of a co-arrival characteristic of the discrete events; a correlation unit configured to detect correlations between the data streams based on resistance changes of the resistive memory elements. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification