Flash memory system
First Claim
Patent Images
1. A system comprising:
- at least two flash memory banks being independently operable by having respective row decoding circuitry and sense amplifier circuitry, a first of the flash memory banks forming a part of a flash memory device of the system, and the flash memory device including;
a clock input configured to receive a clock signal;
a common command, address, data input configured to receive input data, address data and command data, all at different times, and the address data identifying the first flash memory bank as addressed for having an operation carried out thereon;
a first control input configured to receive a first of two control signals;
a second control input configured to receive a second of the two control signals;
circuitry configured to execute the operation on the first flash memory bank corresponding to the command data; and
latch circuitry configured to;
latch the command data while the first of the two control signals is held at an active logic level for at least a duration of time that the command data is received at the common input, andlatch the input data in synchronization with both rising and falling edges of the clock signal; and
a memory controller communicatively coupled to the flash memory device, and the memory controller being configured to source the input data, the address data and the command data to the flash memory device.
3 Assignments
0 Petitions
Accused Products
Abstract
An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
-
Citations
11 Claims
-
1. A system comprising:
-
at least two flash memory banks being independently operable by having respective row decoding circuitry and sense amplifier circuitry, a first of the flash memory banks forming a part of a flash memory device of the system, and the flash memory device including; a clock input configured to receive a clock signal; a common command, address, data input configured to receive input data, address data and command data, all at different times, and the address data identifying the first flash memory bank as addressed for having an operation carried out thereon; a first control input configured to receive a first of two control signals; a second control input configured to receive a second of the two control signals; circuitry configured to execute the operation on the first flash memory bank corresponding to the command data; and latch circuitry configured to; latch the command data while the first of the two control signals is held at an active logic level for at least a duration of time that the command data is received at the common input, and latch the input data in synchronization with both rising and falling edges of the clock signal; and a memory controller communicatively coupled to the flash memory device, and the memory controller being configured to source the input data, the address data and the command data to the flash memory device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
Specification