Semiconductor memory device and memory controller

• US 9,524,792 B2
• Filed: 08/27/2014
• Issued: 12/20/2016
• Est. Priority Date: 03/17/2014
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shirakawa, Masanobu
• Primary Examiner(s): Le, Vu
• Assistant Examiner(s): CHO, SUNG IL
• Application Number:
  US14/470,411
• Publication Number:
  US 20150262699A1
• Time in Patent Office: 846 Days
• Field of Search: 365/185.11, 365/185.17, 365/185.01
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor memory device includes a plurality of string units, each of which includes a plurality of strings of memory cells connected in series, a controller configured to perform an erase operation on the string units, the erase operation including an erase verify operation that is performed per string unit, and a control circuit including a register that stores erase characteristic for at least one of the string units. The control circuit is configured to output the erase characteristic in response to a command from a memory controller.

Claims

1. A memory controller that controls a semiconductor memory device including a plurality of string units, each of which includes a plurality of strings of memory cells connected in series, the memory controller comprising:

a control unit configured to issue a first command including first address data to the semiconductor memory device during a first phase, and a second command including second address data to the semiconductor memory device during a second phase after the first phase,

wherein the second command is a command to perform an erase operation on a block including a plurality of string units indicated by the second address data, and the first command specifies through the first address data whether or not each of the strings units is an erase verify operation target.

2. The memory controller according to claim 1, wherein

the first address data includes a plurality of bit data, each bit data specifying whether or not one of the string units is the erase verify operation target.

3. The memory controller according to claim 1, wherein

the control unit is configured to issue a third command including third address data to perform the erase operation after issuing the second command.

4. The memory controller according to claim 1, wherein

the control unit is configured to issue a third command to the semiconductor memory device to cause the semiconductor memory device to return information about an erase characteristic of each of the string units, and

the information includes an erase loop frequency at the time one of the string units passed the erase verify operation.

5. The memory controller according to claim 4, wherein

the information further includes address data of the one of the string units.

6. The memory controller according to claim 1, wherein the plurality of string units in the block includes a first string unit and a second string unit, and the first address data indicates whether or not the first string unit is an erase verify operation target and whether or not the second string unit is an erase verify operation target.

7. A method of controlling a semiconductor memory device including a plurality of string units, each of which includes a plurality of strings of memory cells connected in series, comprising:

issuing a first command including first address data to the semiconductor memory device during a first phase; and

issuing a second command including second address data to the semiconductor memory device during a second phase after the first phase,

wherein the second command is a command to perform an erase operation on a block including a plurality of string units indicated by the second address data, and the first command specifies through the first address data whether or not each of the strings units is an erase verify operation target.

8. The method according to claim 7, wherein

the first address data includes a plurality of bit data, each bit data specifying whether or not one of the string units is the erase verify operation target.

9. The method according to claim 7, wherein

the control unit is configured to issue a third command including third address data to perform the erase operation after issuing the second command.

10. The method according to claim 7, wherein

the control unit is configured to issue a third command to the semiconductor memory device to cause the semiconductor memory device to return information about an erase characteristic of each of the string units, and

the information includes an erase loop frequency at the time one of the string units passed the erase verify operation.

11. The method according to claim 10, wherein

the information further includes address data of the one of the string units.

12. The method according to claim 7, wherein the plurality of string units in the block includes a first string unit and a second string unit, and the first address data indicates whether or not the first string unit is an erase verify operation target and whether or not the second string unit is an erase verify operation target.