Chip level heat dissipation using silicon

• US 9,524,917 B2
• Filed: 03/18/2015
• Issued: 12/20/2016
• Est. Priority Date: 04/23/2014
• Status: Active Grant

• Current Assignee: Optiz, Inc.
• Original Assignee: Optiz, Inc.
• Inventors: Oganesian, Vage
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US14/662,088
• Publication Number:
  US 20150311137A1
• Time in Patent Office: 643 Days
• Field of Search: 257/433, 257/432, 257/444, 257/706, 257/712, 257/713, 438/64
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4871 Bases, plates or heatsinks
• CPC Class Codes: H01L 23/3672 Foil-like cooling fins or heat sinks being part of lead-frames H01L23/49568
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/3738 Semiconductor materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device that includes a semiconductor chip having a first silicon substrate with opposing first and second surfaces, a semiconductor device formed at or in the first surface, a plurality of first contact pads formed at the first surface which are electrically coupled to the semiconductor device, a layer of thermal conductive material on the second surface, and a plurality of first vias formed partially through the layer of thermal conductive material.

Claims

1. A semiconductor apparatus, comprising:

a semiconductor chip, comprising;

a first silicon substrate with opposing first and second surfaces,

a semiconductor device formed at or in the first surface,

a plurality of first contact pads formed at the first surface which are electrically coupled to the semiconductor device,

a layer of thermal conductive material on the second surface, and

a plurality of first vias formed partially through the layer of thermal conductive material; and

a heat sink that includes;

a second silicon substrate with opposing first and second surfaces,

a plurality of second vias formed into one of the first and second surfaces defining first fins of the second silicon substrate between the second vias,

a layer of thermal conductive material in the second vias,

wherein the second surface of the first silicon substrate is mounted to the first surface of the second silicon substrate.

2. The semiconductor apparatus of claim 1, wherein the plurality of second vias is formed into the first surface of the second silicon substrate.

3. The semiconductor apparatus of claim 2, further comprising:

a cavity formed into the first surface of the second substrate, wherein the semiconductor chip is disposed in the cavity.

4. The semiconductor apparatus of claim 3, wherein the layer of thermal conductive material extends into the cavity.

5. The semiconductor apparatus of claim 2, further comprising:

a plurality of third vias formed into the second surface of the second silicon substrate; and

a second layer of thermal conductive material in the third vias.

6. The semiconductor apparatus of claim 2, further comprising:

a second layer of thermal conductive material on the second surface of the second silicon substrate; and

a plurality of third vias formed partially through the second layer of thermal conductive material.

7. The semiconductor apparatus of claim 5, further comprising:

a plurality of through holes each extending between the first and second surfaces of the second substrate and each lined or filled with thermal conductive material.

8. The semiconductor apparatus of claim 7, wherein each of the through holes is aligned with one of the third vias.

9. The semiconductor apparatus of claim 6, further comprising:

a plurality of through holes each extending between the first and second surfaces of the second substrate and each lined or filled with thermal conductive material.

10. The semiconductor apparatus of claim 7, wherein each of the through holes is aligned with one of the third vias.

11. The semiconductor apparatus of claim 3, further comprising:

a plurality of third vias formed into the second surface of the second silicon substrate defining second fins of the second silicon substrate between the third vias.

12. The semiconductor apparatus of claim 11, further comprising:

a second cavity formed into the second surface of the second substrate.

13. The semiconductor apparatus of claim 1, wherein each of the fins of the second silicon substrate is elongated and extending parallel to the others of the fins.

14. The semiconductor apparatus of claim 1, wherein each of the fins of the second silicon substrate is elongated and extending away from a central portion of the second substrate.

15. The semiconductor apparatus of claim 1, wherein each of the fins of the second silicon substrate is a pillar.