Apparatus and method of three dimensional conductive lines

• US 9,524,920 B2
• Filed: 11/12/2013
• Issued: 12/20/2016
• Est. Priority Date: 11/12/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chih-Yu, Lin, Kao-Cheng, Wang, Li-Wen, Chen, Yen-Huei
• Primary Examiner(s): Sefer, A.
• Application Number:
  US14/077,252
• Publication Number:
  US 20150130068A1
• Time in Patent Office: 1,134 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/10 including a plurality of individual components in a repetitive configuration
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

Claims

1. An inter-tier memory column, comprising:

a first segment disposed within a first tier of a three-dimensional integrated circuit (3D IC), the first segment comprising a first bit line, a first bit line bar, and a first plurality of memory cells, said first plurality of memory cells electrically connected to said first bit line and said first bit line bar;

a second segment disposed within a second tier of the 3D IC, comprising a second bit line, a second bit line bar, and a second plurality of memory cells, said second plurality of memory cells electrically connected to said second bit line and said second bit line bar; and

wherein said first bit line is electrically connected to said second bit line by a conductive member extending continuously from said first bit line to said second bit line, and said first bit line bar is electrically connected to said second bit line bar by a conductive member extending continuously from said first bit line bar to said second bit line bar.

2. The inter-tier memory column of claim 1, wherein said first segment and said second segment are aligned parallel to each other.

3. The inter-tier memory column of claim 1, further comprising:

an inter-tier word line electrically connected across said first segment and said second segment.

4. The inter-tier memory column of claim 1,

wherein said first bit line comprises a first bit line part and a horizontally offset second bit line part, said second bit line comprises a third bit line part and a horizontally offset fourth bit line part;

and

wherein said horizontally offset second bit line part and said horizontally offset fourth bit line part are electrically connected by an inter-tier via.

5. The inter-tier memory column of claim 4,

wherein said first bit line bar comprises a first bit line bar part and a horizontally offset second bit line bar part, said second bit line bar comprises a third bit line bar part and a horizontally offset fourth bit line bar part;

and

wherein said horizontally offset second bit line bar part and said horizontally offset fourth bit line bar part are electrically connected by an inter-tier via.

6. A three-dimensional integrated circuit (3D IC) comprising:

a first memory cell segment and a second memory cell segment, disposed within a first tier of the 3D IC;

a third memory cell segment and a fourth memory cell segment, disposed within a second tier of the 3D IC;

wherein each of said first, second, third, and fourth memory cell segments comprise a bit line, a bit line bar, and at least one memory cell electrically connected to said bit line and said bit line bar; and

wherein a first conductive member extends continuously from a bit line in the first tier to a bit line in the second tier, and wherein a second conductive member extends continuously from a bit line bar in the first tier to a bit line bar in the second tier.

7. The 3D IC of claim 6, wherein the first conductive member is a word line.

8. The 3D IC of claim 6, wherein the first conductive member is a bit line formed by electrically connecting the bit line and bit line bar of the first memory cell segment with respective bit line and bit line bar of the fourth memory cell segment.

9. The 3D IC of claim 8 wherein the bit line and bit line bar of the second memory cell segment are electrically connected with respective bit line and bit line bar of the third memory cell segment.

10. The 3D IC of claim 9, further comprising:

a fifth memory cell segment and a sixth memory cell segment, disposed within a third tier of the 3D IC;

wherein the fifth memory cell segment is electrically connected to the first memory cell segment and the third memory cell segment, and the sixth memory cell segment is electrically connected to the second memory cell segment and the fourth memory cell segment.

11. A three-dimensional integrated circuit (3D IC) comprising:

a first memory cell segment and a second memory cell segment, disposed within a first tier of the 3D IC;

a third memory cell segment and a fourth memory cell segment, disposed within a second tier of the 3D IC;

wherein each of said first, second, third, and fourth memory cell segments comprise a bit line, a bit line bar, and at least one memory cell electrically connected to said bit line and said bit line bar;

wherein each of said bit lines are aligned parallel to and disposed on a first side of a first longitudinal axis and each of said bit lines bar are aligned parallel to and disposed on a second side of said first longitudinal axis; and

wherein a first conductive member extends continuously from a bit line in the first tier to a bit line in the second tier, and wherein a second conductive member extends continuously from a bit line bar in the first tier to a bit line bar in the second tier.

12. The 3D IC of claim 11 wherein an inter-tier word line is electrically connected across a memory cell segment disposed within the first tier and a memory cell segment disposed within the second tier.

13. The 3D IC of claim 12 wherein each of said first, second, third, and fourth memory cell segments comprises a plurality of memory cells electrically connected to the respective first bit line and second bit line.

14. The 3D IC of claim 11 further comprising:

a third conductive member extending continuously from a bit line of said second memory cell segment to a bit line of said third memory cell segment; and

a fourth conductive member extending continuously a bit line bar of said second memory cell segment to a bit line bar of said third memory cell segment.