System on integrated chips and methods of forming same

• US 9,524,959 B1
• Filed: 12/04/2015
• Issued: 12/20/2016
• Est. Priority Date: 11/04/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeh, Sung-Feng, Yu, Chen-Hua, Chen, Ming-Fa
• Primary Examiner(s): Menz, Douglas
• Application Number:
  US14/960,225
• Time in Patent Office: 382 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/08 of an individual bonding area
• CPC Class Codes: H01L 2224/08121 the connected bonding areas being not aligned with respect to each other
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/09517 including bonding areas providing primarily mechanical support
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/29076 being mutually engaged together, e.g. through inserts
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/29186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32227 the layer connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73209 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/73251 : on different surfaces
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2224/80001 : by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/80006 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/80895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/8203 : Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/83005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/83896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/92124 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/315 : the encapsulation having a cavity
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10252 : Germanium [Ge]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10271 : Silicon-germanium [SiGe]
• CPC Class Codes: H01L 2924/10272 : Silicon Carbide [SiC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/10331 : Gallium phosphide [GaP]
• CPC Class Codes: H01L 2924/10332 : Indium antimonide [InSb]
• CPC Class Codes: H01L 2924/10333 : Indium arsenide [InAs]
• CPC Class Codes: H01L 2924/10335 : Indium phosphide [InP]
• CPC Class Codes: H01L 2924/10338 : Indium gallium phosphide [InGaP]
• CPC Class Codes: H01L 2924/10339 : Aluminium indium arsenide [AlInAs]
• CPC Class Codes: H01L 2924/10342 : Gallium arsenide phosphide [GaAsP]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/141 : Analog devices
• CPC Class Codes: H01L 2924/143 : Digital devices
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1816 : Exposing the passive side of the semiconductor or solid-state body
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

Claims

1. A method for forming a semiconductor package comprising:

attaching a first die to a first carrier;

depositing a first isolation material around the first die;

after depositing the first isolation material, bonding a second die to the first die, wherein bonding the second die to the first die comprises forming a dielectric-to-dielectric bond;

removing the first carrier; and

forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die, wherein the fan-out RDLs are electrically connected to the first die and the second die.

2. The method of claim 1 further comprising depositing a bonding layer over the first die and the first isolation material, wherein bonding the second die comprises fusion bonding the second die to the bonding layer.

3. The method of claim 1 further comprising:

depositing a bonding layer over the first die and the first isolation material; and

forming first conductive features at a top surface of the bonding layer, wherein bonding the second die comprises hybrid bonding the second die to the bonding layer.

4. The method of claim 1 further comprising depositing a second isolation material around the second die.

5. The method of claim 4, wherein depositing the second isolation material comprises depositing the second isolation material so that a lateral portion of the second isolation material directly over the first isolation material has substantially a same thickness as a vertical portion of the second isolation material on a sidewall of the second die.

6. The method of claim 5 further comprising forming a third isolation material over and contacting the second isolation material, wherein the third isolation material and the second isolation material comprise different materials.

7. The method of claim 1 further comprising disposing a dummy die adjacent the first die or the second die.

8. The method of claim 1 further comprising after bonding the second die attaching a second carrier to an opposing surface of the second die as the first die.

9. The method of claim 1 further comprising forming a through-via extending through the first isolation material and electrically connecting the fan-out RDLs to the second die.

10. The method of claim 1, wherein attaching the first die to the first carrier comprises attaching the first die to the first carrier using a release layer comprising an alignment mark.

11. A method comprising:

attaching a first die to a first carrier;

forming a first isolation material extending along sidewalls of the first die;

forming a bonding layer over the first die and the first isolation material;

bonding a second die directly to the bonding layer;

forming a second isolation material extending along sidewalls of the second die;

attaching a second carrier over the second die;

removing the first carrier;

forming a through via (TV) extending through the first isolation material and electrically connected to the second die; and

forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die, wherein the fan-out RDLs are electrically connected to the first die and the through via.

12. The method of claim 11, wherein forming the second isolation material comprises depositing a lateral portion of the second isolation material on the bonding layer to have a same thickness as a vertical portion of the second isolation material on a sidewall of the second die.

13. The method of claim 12 further comprising planarizing the second isolation material to expose the second die, wherein attaching the second carrier forms a cavity between the second carrier and the second isolation material.

14. The method of claim 12 further comprising forming a third isolation material on the second isolation material, wherein a surface of the third isolation material opposite the second isolation material is substantially level.

15. The method of claim 12, wherein the first isolation material and the second isolation material comprise different materials.

16. A method comprising:

attaching a first die on a first carrier;

attaching a second die on a second carrier;

bonding the first die to the second die while the first die is attached to the first and the second die is attached to the second carrier;

dispensing a molding compound around the first die and the second die, wherein the molding compound is dispensed between the first carrier and the second carrier;

removing the second carrier to expose a surface of the second die opposite the first die; and

forming fan-out redistribution layers over the second die and the first die, wherein the fan-out redistribution layers are electrically connected to the first die and the second die.

17. The method of claim 16, wherein bonding the first die to the second die comprises a hybrid bonding process.

18. The method of claim 16, further comprising forming a conductive via adjacent the second die and extending through a portion of the molding compound, wherein the conductive via is electrically connected to a first conductive feature in the first die.

19. The method of claim 18, wherein the conductive via contacts the first conductive feature in the first die and a second conductive feature in the fan-out redistribution layers.

20. The method of claim 16, wherein the second die comprises a through-via extending through a semiconductor substrate of the second die, and wherein forming the fan-out redistribution layers comprises forming a redistribution line on the semiconductor substrate of the second die and contacting the through-via.