Asymmetric semiconductor memory device having electrically floating body transistor
First Claim
1. An asymmetric semiconductor memory cell comprising:
- a floating body region having a first conductivity type selected from n-type conductivity type and p-type conductivity type;
said floating body region comprising means for storing a charge or lack of charge as a volatile memory indicative of a state of the asymmetric semiconductor memory cell;
a first region having said first conductivity type, wherein said first conductivity type of said first region is and being in direct contact with said first conductivity type of said floating body region;
a gate positioned above said floating body region; and
a second region in electrical contact with said floating body region and spaced apart from said first region, said second region having a second conductivity type selected from said n-type and said p-type conductivity type, said second conductivity type being different from said first conductivity type.
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Abstract
Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.
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Citations
20 Claims
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1. An asymmetric semiconductor memory cell comprising:
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a floating body region having a first conductivity type selected from n-type conductivity type and p-type conductivity type;
said floating body region comprising means for storing a charge or lack of charge as a volatile memory indicative of a state of the asymmetric semiconductor memory cell;a first region having said first conductivity type, wherein said first conductivity type of said first region is and being in direct contact with said first conductivity type of said floating body region; a gate positioned above said floating body region; and a second region in electrical contact with said floating body region and spaced apart from said first region, said second region having a second conductivity type selected from said n-type and said p-type conductivity type, said second conductivity type being different from said first conductivity type. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit comprising:
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a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each said memory cell comprising; a floating body region having a first conductivity type selected from n-type conductivity type and p-type conductivity type;
said floating body region comprising means for storing a charge or lack of charge indicative of a state of said memory cell;a first region in electrical contact with said floating body region having a second conductivity type selected from n-type conductivity type and p-type conductivity type, and wherein said second conductivity type is different from said first conductivity type; a second region in electrical contact with said floating body region having said second conductivity type and being spaced apart from said first region; wherein one of said first region or said second region is connected to a bit line; a plurality of asymmetric memory cells configured for use as reference cells, each said asymmetric memory cell comprising; a second floating body region having said first conductivity type; a third region in electrical contact with said second floating body region having said first conductivity type; a fourth region in electrical contact with said second floating body region having said second conductivity type and spaced apart from said third region; wherein said fourth region is connected to a reference bit line; and a plurality of sensing circuits connected to said bit line and said reference bit line. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. An integrated circuit comprising:
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a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each said memory cell comprising; a floating body region having a first conductivity type selected from n-type conductivity type and p-type conductivity type;
each said floating body region comprising means for storing a charge or lack of charge indicative of a state of each said memory cell, respectively;a first region in electrical contact with said floating body region and having a second conductivity type selected from n-type conductivity type and p-type conductivity type, said second conductivity type being different from said first conductivity type; and a second region in electrical contact with said floating body region, said second region having said second conductivity type and being spaced apart from said first region; a plurality of asymmetric memory cells configured for use as reference cells, each said asymmetric memory cell comprising; a second floating body region having a first conductivity type selected from n-type conductivity type and p-type conductivity type; a third region in electrical contact with said second floating body region and having said first conductivity type; a fourth region in electrical contact with said second floating body region, said fourth region having said second conductivity type and being spaced apart from said third region; wherein said third region is connected to a sense line; a substrate; a buried layer in said substrate, wherein a portion of said substrate is separated from said floating body region by said buried layer; and a control circuit configured to provide electrical signals to said buried layer region, wherein said control circuit is connected to said sense line. - View Dependent Claims (17, 18, 19, 20)
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Specification