Fabricating method of trench gate metal oxide semiconductor field effect transistor

• US 9,525,037 B2
• Filed: 06/29/2015
• Issued: 12/20/2016
• Est. Priority Date: 10/18/2012
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Peng, Chun-Hong, Lai, Yu-Hsi
• Primary Examiner(s): Tran, Thanh Y
• Assistant Examiner(s): Hoque, Mohammad M
• Application Number:
  US14/754,636
• Publication Number:
  US 20150318366A1
• Time in Patent Office: 540 Days
• Field of Search: 257/330, 438/667
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0223 formation by oxidation, e.g. oxidation of the substrate
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31105 Etching inorganic layers
• CPC Class Codes: H01L 21/32115 Planarisation
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench gate metal oxide semiconductor field effect transistor includes a substrate and a gate. The substrate has a trench. The trench is extended downwardly from a surface of the substrate. The gate includes an insertion portion and a symmetrical protrusion portion. The insertion portion is embedded in the trench. The symmetrical protrusion portion is symmetrically protruded over the surface of the substrate.

Claims

1. A method for fabricating a trench gate metal oxide semiconductor field effect transistor, the method comprising steps of:

providing a substrate having a source region;

forming an oxide layer on the substrate;

forming a hard mask layer on the oxide layer;

performing an etching process to remove a part of the hard mask layer, a part of the oxide layer, a part of the substrate to form a trench in the substrate penetrating the source region;

performing an etching back process to remove a part of the remaining hard mask layer to expose a part of the oxide layer;

performing a thermal oxidation process to form a gate dielectric layer only on a sidewall of the trench;

forming a conductive layer covering on the hard mask layer and the exposed part of the oxide layer, and filling the conductive layer into the trench;

performing a chemical mechanical polishing process to remove a portion of the conductive layer on the hard mask layer by using the hard mask layer as a stop layer and leave behind a T-shaped portion of the conductive layer with an insertion portion embedded in the trench and a symmetrical protrusion portion on the substrate; and

forming a contact plug on the surface of the substrate contacting the T-shaped portion of the conductive layer.

2. The method according to claim 1, wherein the oxide layer is a pad silicon oxide layer.

3. The method according to claim 1, wherein after the hard mask layer is formed, the method further comprises a step of forming a sacrificial layer on the hard mask layer.

4. The method according to claim 1, wherein the hard mask layer is a silicon oxide layer or a silicon nitride layer.

5. The method according to claim 2, wherein the symmetrical protrusion portion of the conductive layer covering a portion of the pad silicon oxide layer on the substrate.

6. The method according to claim 1, wherein the step of performing a thermal oxidation process to form the gate dielectric layer is performed directly after the step of performing the etching back process.

7. The method according to claim 1, wherein the symmetrical protrusion portion on the substrate covering a portion of the source region.

8. The method according to claim 1, wherein the the symmetrical protrusion portion is symmetrical with respect to the insertion portion on the substrate.

9. The method according to claim 1, wherein the etching back process is a wet etching process.

10. The method according to claim 1, wherein the contact plug is attached to the symmetrical protrusion portion of the T-shaped portion of the conductive layer.

11. The method according to claim 1, after the step of performing the chemical mechanical polishing process and before the step of forming the contact plug, further comprising:

forming a dielectric material layer over the surface of the substrate and the T-shaped portion of the conductive layer; and

removing a portion of the dielectric material layer and a portion of the oxide layer.