Semiconductor device and driving method thereof

• US 9,525,051 B2
• Filed: 06/16/2015
• Issued: 12/20/2016
• Est. Priority Date: 08/06/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Inoue, Hiroki, Kato, Kiyoshi, Matsuzaki, Takanori, Nagatsuka, Shuhei
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US14/740,688
• Publication Number:
  US 20150311323A1
• Time in Patent Office: 553 Days
• Field of Search: 365/149, 365/185.1, 365/185.14, 365/185.26
• US Class Current: 1/1
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/425 producing ion implantation
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78651 Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/70 : the floating gate being an electrode shared by two or more components
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer over an insulating surface, the oxide semiconductor layer including a channel formation region, the oxide semiconductor layer containing indium, tin and zinc;

implanting oxygen ions into the oxide semiconductor layer;

performing a first heat treatment on the oxide semiconductor layer in an atmosphere containing nitrogen;

performing a second heat treatment on the oxide semiconductor layer in an atmosphere containing oxygen so that the oxide semiconductor layer includes excess oxygen and the oxide semiconductor layer is capable of compensating an oxygen deficiency in the oxide semiconductor layer;

wherein the second heat treatment is performed after the first heat treatment.

2. The method for manufacturing a semiconductor device according to claim 1, further comprising the steps of:

forming a gate electrode layer so that the oxide semiconductor layer and the gate electrode layer overlap each other;

forming a first insulating layer including the insulating surface between the gate electrode layer and the oxide semiconductor layer;

forming a source electrode layer and a drain electrode layer which are electrically connected to the oxide semiconductor layer; and

forming a second insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer,

wherein the oxide semiconductor layer is formed by sputtering method.

3. The method for manufacturing a semiconductor device, according to claim 2,

wherein the first insulating layer is in direct contact with the oxide semiconductor layer, and

wherein the first insulating layer includes a region where the proportion of oxygen is higher than that in the stoichiometric composition.

4. The method for manufacturing a semiconductor device, according to claim 1, wherein a temperature of the first heat treatment is higher than or equal to 250°

C. and lower than or equal to 750°

C.

5. The method for manufacturing a semiconductor device, according to claim 1, further comprising the steps of:

forming a p-channel transistor wherein a gate of the p-channel transistor is electrically connected to a transistor comprising the oxide semiconductor layer, and

forming a bit line electrically connected to one of a source and a drain of the transistor and one of a source and a drain of the p-channel transistor.

6. The method for manufacturing a semiconductor device, according to claim 5, wherein a channel region of the p-channel transistor includes silicon.

7. The method for manufacturing a semiconductor device, according to claim 1, further comprising the steps of:

forming a p-channel transistor wherein a gate of the p-channel transistor is electrically connected to a transistor comprising the oxide semiconductor layer,

forming a bit line electrically connected to one of a source and a drain of the transistor and one of a source and a drain of the p-channel transistor, and

forming a capacitor element wherein one electrode of the capacitor element is electrically connected to the gate of the p-channel transistor and the other of the source and the drain of the transistor.

8. The method for manufacturing a semiconductor device, according to claim 1, further comprising the steps of:

forming a p-channel transistor wherein a gate of the p-channel transistor is electrically connected to a transistor comprising the oxide semiconductor layer, and

forming a bit line electrically connected to one of a source and a drain of the transistor and one of a source and a drain of the p-channel transistor.

9. The method for manufacturing a semiconductor device, according to claim 8, wherein a channel region of the p-channel transistor includes silicon.

10. The method for manufacturing a semiconductor device, according to claim 1, further comprising the steps of:

forming a p-channel transistor wherein a gate of the p-channel transistor is electrically connected to a transistor comprising the oxide semiconductor layer,

forming a bit line electrically connected to one of a source and a drain of the transistor and one of a source and a drain of the p-channel transistor, and

forming a capacitor element wherein one electrode of the capacitor element is electrically connected to the gate of the p-channel transistor and the other of the source and the drain of the transistor.

11. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer over an insulating surface, the oxide semiconductor layer including a channel formation region, the oxide semiconductor layer containing indium, tin and zinc;

implanting oxygen ions into the oxide semiconductor layer;

performing a first heat treatment on the oxide semiconductor layer in an atmosphere containing nitrogen;

performing a second heat treatment on the oxide semiconductor layer in an atmosphere containing oxygen so that the oxide semiconductor layer includes excess oxygen and the oxide semiconductor layer is capable of compensating an oxygen deficiency in the oxide semiconductor layer; and

performing a oxygen doping into the oxide semiconductor layer,

wherein the second heat treatment is performed after the first heat treatment.

12. The method for manufacturing a semiconductor device according to claim 11, further comprising the steps of:

forming a gate electrode layer so that the oxide semiconductor layer and the gate electrode layer overlap each other;

forming a first insulating layer including the insulating surface between the gate electrode layer and the oxide semiconductor layer;

forming a source electrode layer and a drain electrode layer which are electrically connected to the oxide semiconductor layer; and

forming a second insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer,

wherein the oxide semiconductor layer is formed by sputtering method.

13. The method for manufacturing a semiconductor device, according to claim 12,

wherein the first insulating layer is in direct contact with the oxide semiconductor layer, and

wherein the first insulating layer includes a region where the proportion of oxygen is higher than that in the stoichiometric composition.

14. The method for manufacturing a semiconductor device, according to claim 11, wherein a temperature of the first heat treatment is higher than or equal to 250°

C. and lower than or equal to 750°

C.

15. The method for manufacturing a semiconductor device, according to claim 11, wherein the step of the oxygen doping into the oxide semiconductor layer is performed using an ion implantation method or an ion doping method.