Power switching systems comprising high power e-mode GaN transistors and driver circuitry

• US 9,525,413 B2
• Filed: 04/14/2016
• Issued: 12/20/2016
• Est. Priority Date: 03/12/2014
• Status: Active Grant

• Current Assignee: GaN Systems Inc. (Infineon Technologies AG)
• Original Assignee: GaN Systems Inc. (Infineon Technologies AG)
• Inventors: Scott, Iain H., Roberts, John
• Primary Examiner(s): LUU, AN T
• Application Number:
  US15/099,459
• Publication Number:
  US 20160233859A1
• Time in Patent Office: 250 Days
• Field of Search: 327108-109, 327/112, 327/419, 327/427
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 5/08 by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30

Abstract

Driver circuitry for switching systems comprising enhancement mode (E-Mode) GaN power transistors with low threshold voltage is disclosed. An E-Mode high electron mobility transistor (HEMT) D3 has a monolithically integrated GaN driver, comprising smaller E-Mode GaN HEMTs D1 and D2, and a discrete dual-voltage pre-driver. In operation, D1 provides the gate drive voltage to the gate of the GaN switch D3, and D2 clamps the gate of the GaN switch D3 to the source, via an internal source-sense connection closely coupling the source of D3 and the source of D2. An additional source-sense connection is provided for the pre-driver. Boosting the drive voltage to the gate of D1 produces firm and rapid pull-up of D1 and D3 for improved switching performance at higher switching speeds. High current handling components of the driver circuitry are integrated with the GaN switch and closely coupled to reduce inductance, while the discrete pre-driver can be thermally separated from the GaN chip.

Claims

1. A GaN transistor switching device comprising:

an enhancement mode (E-Mode) GaN switch having an integrated GaN driver;

the E-Mode GaN switch comprising a GaN transistor switch D3 fabricated on a substrate and the integrated GaN driver being integrated monolithically with the GaN transistor switch D3 on the substrate, wherein;

the integrated GaN driver comprises a first, pull-up, E-Mode GaN driver transistor D1 and a second, pull-down, E-Mode GaN driver transistor D2, the drain of the D1 being coupled to Vcc, and the source of D1 being coupled to the drain of D2 at a node N, and node N being coupled to the gate of D3, and an internal source-sense connection closely coupling the source of D3 and the source of D2, such that the first transistor D1 operates to deliver a drive voltage to the gate of the GaN transistor switch D3, and the second transistor D2 operates to clamp the gate of the GaN transistor switch D3 to Vss by means of the internal source-sense connection SS_internal;

inputs for coupling to a pre-driver supplying gate drive voltages to the gates of D1 and D2 and, optionally, to the gate of D3, and

an external source-sense connection SS_external for coupling to the pre-driver.

2. The device of claim 1 wherein D3 is a large gate width E-Mode GaN HEMT having a threshold voltage of ˜

1.5V and D1 and D2 are smaller gate width E-Mode GaN HEMTs.

3. A method of operating the GaN switching device D3 having integrated GaN driver circuitry comprising D1 and D2, as defined in claim 1, comprising:

providing, from a pre-driver, dual voltage drive outputs comprising a first drive voltage 0-Vcc₁ for driving the gate of D1 and a second drive voltage 0-Vcc₂ for driving the gate of D2, wherein Vcc₁ is greater than Vcc₂.

4. A GaN power switching system comprising:

an enhancement mode (E-Mode) GaN switch and driver circuitry comprising an integrated GaN driver and a discrete pre-driver;

the E-Mode GaN switch comprising a GaN transistor switch (D3) fabricated on a first substrate and the integrated GaN driver being integrated monolithically with the GaN transistor D3 on the GaN chip, wherein;

the integrated GaN driver comprises a first, pull-up, E-mode GaN driver transistor D1 and a second, pull-down, E-mode GaN driver transistor D2, the drain of D1 being coupled to the supply voltage Vcc, and the source of D1 being coupled to the drain of D2 at node N, which is coupled to the gate of D3, such that the first transistor D1 operates to deliver a drive voltage to the gate of the GaN transistor switch D3, and an internal source-sense connection closely coupling the source of D3 and the source of D2, such that the second transistor D2 operates to clamp the gate of the GaN transistor switch D3 to source by means of the internal source-sense connection SS_internal;

external gate inputs for supplying gate drive voltages from the pre-driver to each of the gates of D1 and D2, and optionally to the gate of D3; and

an external source-sense connection SS_external for coupling to the pre-driver circuit; and

the pre-driver is fabricated on a second, pre-driver, substrate 102, the pre-driver having an input for receiving an input voltage Vin and outputs for delivering gate drive voltages to the gate connections of each of GaN driver transistors D1 and D2 of the integrated GaN driver.

5. The system of claim 4, wherein the pre-driver further comprises an output for delivering a gate drive voltage to the gate of D3.

6. The system of claim 4, wherein D3 is a large gate width E-Mode GaN HEMT having a threshold voltage of ˜

1.5V and D1 and D2 are smaller gate width E-Mode GaN HEMTs.

7. The system of claim 6, wherein the pre-driver is a dual voltage pre-driver configured with non-inverting pre-driver circuitry to supply a first drive voltage 0-Vcc₁ to the gate of D1, inverting pre-driver circuitry to supply a second drive voltage 0-Vcc₂ to the gate of D2, and when there is a gate connection to the gate of D3, non-inverting pre-driver circuitry to supply the second drive voltage 0-Vcc₂ to the gate of D3, and wherein the first supply voltage Vcc₁ is higher than the second supply voltage Vcc₂.

8. The system of claim 7 wherein the pre-driver supplies a gate drive voltage Vcc₂ of 0-6V and a gate drive voltage Vcc₁ of 0-10V.

9. The system of claim 7 wherein the pre-driver comprises a voltage doubler that develops a voltage supply Vcc₁ of 12V from a voltage supply Vcc₂ of 6V.

10. The system of claim 4 wherein the pre-driver comprises first, second and third discrete pre-driver components Pd1, Pd2 and Pd3 coupled in parallel paths between the input for Vin and respective outputs for gate voltages to D1, D2 and D3;

Pd1 and Pd2 being non-inverting and configured so that when Vin is high a gate drive voltage is supplied to turn on the driver transistor D1 which provides a gate voltage to the gate of D3 to turn on the power switch D3, and Pd3 being an inverting element configured so that when Vin is low a gate drive voltage is supplied to D2 to turn on D2 to clamp the power switch D3 off.

11. The system of claim 10 wherein the Pd1 pre-driver is a 10V non-inverting driver and Pd2 is a 6V non-inverting driver and Pd3 is a 6V inverting driver.

12. The system of claim 10 wherein the discrete pre-driver components comprise CMOS pre-drivers.

13. The system of claim 4 wherein the pre-driver provides a single supply voltage Vcc, first, second and third pre-driver circuit components Pd1, Pd2 and Pd3, and a large p-channel MOSFET M1, wherein the source of the M1 is coupled to Vcc, the drain of the MOSFET M1 coupled to the gate of D3 for pulling the gate to the power supply voltage Vcc;

Pd1 being a non-inverting driver being coupled between the input for Vin and output to the gate of D1 for driving the gate of D1;

Pd3 being an inverting driver being coupled between the input for Vin and output to the gate of D2 for driving the gate of D2; and

Pd2 being an inverting driver coupled between the input for Vin and the gate of the p-channel MOSFET M1 for driving the gate of M1, such that M1 drives the gate of D3.

14. The system of any claim 4 wherein the pre-driver comprises an integrated circuit using a single supply voltage Vcc;

first, second and third integrated pre-driver circuit elements Pd1, Pd2 and Pd3, and a large p-channel MOSFET structure M1, wherein the source of the M1 is coupled to Vcc, the drain of the MOSFET is coupled to the gate of D3 for pulling the gate to the power supply voltage Vcc;

Pd1 being a non-inverting driver being coupled between the input for Vin and output to the gate of D1 for driving the gate of D1;

Pd3 being an inverting driver being coupled between the input for Vin and output to the gate of D2 for driving the gate of D2; and

Pd2 being an inverting driver coupled between the input for Vin and the gate of the p-channel MOSFET M1, such that M1 drives the gate of M1.

15. The system of claim 4 wherein the pre-driver comprises voltage boost circuitry for developing a supply voltage Vcc₁ from a supply voltage Vcc, wherein Vcc₁>

Vcc; and

wherein the pre-driver is configured to provide a first output drive voltage of 0-Vcc₁ to the gate of D1 and a second output voltage 0-Vcc to the gate of D2.

16. The system of claim 15 wherein the pre-driver provides outputs to the gates of D1 and D3, and wherein the pre-driver further comprises circuit elements P1, N1 and N2, P2, P3 and P4;

N3 and N4, N5 and N6;

said elements being coupled as illustrated in FIG. 10, such that;

when Vin is low and less than Vtp+Vtn+Vth_high, P1 and N1 conduct current I and D2 is on, which holds D3 off; and

when Vin is high and more than Vtp+Vtn+Vth_low, N2 and P2 conduct current I and P4 and P3 are on and provide gate current to D1, which provides gate current to D3, such that D3 is on; and

N3, N4, and N5, N6 being coupled to ensure D2 and D1 are not on at the same time, such that while D1 is on, D2 must be off and so the current in P2 turns on N3 and N4, holding D2 off;

similarly, to ensure D1 is off when D2 is on, current flowing in P1 turns on N5 and N6, thus sinking any current on gate of D1, and holding D1 off.