Phase locked loop for preventing harmonic lock, method of operating the same, and devices including the same

• US 9,525,545 B2
• Filed: 02/17/2014
• Issued: 12/20/2016
• Est. Priority Date: 02/25/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Oh, Woon Taek, Kim, Jin Ho, Kim, Tae Jin, Lee, Jae Youl, Chang, Young Hwan
• Primary Examiner(s): Houston, Adam
• Application Number:
  US14/182,029
• Publication Number:
  US 20140240371A1
• Time in Patent Office: 1,037 Days
• Field of Search: 327147-149, 327156-158
• US Class Current: 1/1
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 5/02 characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A phase locked loop includes a voltage controlled oscillator including a plurality of delay cells configured to respectively generate a plurality of clock signals having different phases and a harmonic lock detector configured to detect harmonic lock in the voltage controlled oscillator and to generate a reset signal in response. Remaining ones of the delay cells other than a first delay cell among the plurality of delay cells are reset in response to the reset signal.

Claims

1. A phase locked loop comprising:

a voltage controlled oscillator comprising a plurality of delay cells configured to respectively generate a plurality of clock signals having respective different phases; and

a harmonic lock detector configured to detect harmonic lock of the voltage controlled oscillator and to generate a reset signal in response to detecting harmonic lock of the voltage controlled oscillator;

wherein the plurality of delay cells comprise a first delay cell and a plurality of remaining delay cells; and

wherein the remaining delay cells are reset in response to the reset signal and the first delay cell is not reset in response to the reset signal.

2. The phase locked loop of claim 1, wherein the harmonic lock detector is configured to generate the reset signal in response to more than one of the plurality of clock signals.

3. The phase locked loop of claim 1, wherein each of the remaining delay cells comprises:

a unit delay cell;

a bias current generator coupled to the unit delay cell; and

a reset switch coupled to the bias current generator.

4. The phase locked loop of claim 3, wherein the reset switch is configured to control connection between the bias current generator and an operating voltage supply terminal of the unit delay cell in response to the reset signal.

5. The phase locked loop of claim 3, wherein the reset switch is configured to control connection between the bias current generator and a ground in response to the reset signal.

6. The phase locked loop of claim 1, wherein when the reset signal is deactivated, at least one of the remaining delay cells generates a realigned clock signal based on a clock signal output from a previous delay cell of the plurality of delay cells.

7. A phase locked loop, comprising:

a voltage controlled oscillator comprising a plurality of delay cells coupled in series that generate respective clock signals, the plurality of delay cells including a first delay cell and a plurality of remaining delay cells; and

a harmonic lock detector configured to detect harmonic lock of the voltage controlled oscillator and to reset the remaining delay cells in response to detecting harmonic lock of the voltage controlled oscillator;

wherein the first delay cell is not reset by the harmonic lock detector in response to detecting harmonic lock of the voltage controlled oscillator.

8. A method of operating a phase locked loop, the method comprising:

detecting harmonic lock of a voltage controlled oscillator in the phase locked loop;

generating a reset signal in response to detecting harmonic lock of the voltage controlled oscillator; and

resetting a plurality of delay cells connected in series in the voltage controlled oscillator other than a first delay cell in the voltage controlled oscillator in response to the reset signal.