Detecting disconnection fault in device monitoring circuit connected in multiple stages for battery cells connected in series
First Claim
1. An electrical storage device monitoring circuit, comprising:
- a 3-state buffer configured to switch between a high output state and a low output state based on a flag output delivered from a previous electrical storage device monitoring circuit at a front stage, and also configured to detect a disconnection between the electrical storage device monitoring circuit and the previous electrical storage device monitoring circuit at the front stage;
a detection circuit configured to monitor an electrical storage device to detect whether the electrical storage device is normal or abnormal; and
an output circuit configured to deliver the flag output to a subsequent electrical storage device monitoring circuit at a next stage based on an input of the 3-state buffer and a detection result of the detection circuit.
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Accused Products
Abstract
An electrical storage device monitoring circuit includes a 3-state buffer configured to switch between a high output state and a low output state based on a flag output delivered from a previous electrical storage device monitoring circuit at a front stage, and also configured to detect a disconnection between the current electrical storage device monitoring circuit and the previous electrical storage device monitoring circuit at the front stage; a detection circuit configured to monitor an electrical storage device to detect whether the electrical storage device is normal or abnormal; and an output circuit configured to deliver the flag output to a subsequent electrical storage device monitoring circuit at a next stage based on an input of the 3-state buffer and a detection result of the detection circuit.
28 Citations
9 Claims
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1. An electrical storage device monitoring circuit, comprising:
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a 3-state buffer configured to switch between a high output state and a low output state based on a flag output delivered from a previous electrical storage device monitoring circuit at a front stage, and also configured to detect a disconnection between the electrical storage device monitoring circuit and the previous electrical storage device monitoring circuit at the front stage; a detection circuit configured to monitor an electrical storage device to detect whether the electrical storage device is normal or abnormal; and an output circuit configured to deliver the flag output to a subsequent electrical storage device monitoring circuit at a next stage based on an input of the 3-state buffer and a detection result of the detection circuit. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An electrical storage device monitoring circuit comprising:
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a first 3-state buffer configured to switch between a high output state and a low output state based on a first flag output delivered from a previous electrical storage device monitoring circuit at a front stage, and also configured to detect a disconnection between the electrical storage device monitoring circuit and the previous electrical storage device monitoring circuit at the front stage; a second 3-state buffer configured to switch between a high output state and a low output state based on a second flag output delivered from the previous electrical storage device monitoring circuit at the front stage, and also configured to detect the disconnection between the electrical storage device monitoring circuit and the previous electrical storage device monitoring circuit at the front stage; a detection circuit configured to monitor an electrical storage device to detect whether the electrical storage device is normal or abnormal; a first output circuit configured to deliver the first flag output to a subsequent electrical storage device monitoring circuit at a next stage based on an input of the first 3-state buffer and a detection result of the detection circuit; and a second output circuit configured to deliver the second flag output to the subsequent electrical storage device monitoring circuit at the next stage based on the input of the first 3-state buffer and an input of the second 3-state buffer. - View Dependent Claims (8, 9)
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Specification