Method and apparatus for memory allocation in a multi-node system

• US 9,529,532 B2
• Filed: 03/07/2014
• Issued: 12/27/2016
• Est. Priority Date: 03/07/2014
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cavium, LLC (Marvell Technology Group Limited)
• Inventors: Kessler, Richard E., Snyder, Wilson P. II
• Primary Examiner(s): SUN, SCOTT C
• Application Number:
  US14/201,594
• Publication Number:
  US 20150253997A1
• Time in Patent Office: 1,026 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device

Abstract

According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of memory allocation in the multi-chip system comprises managing, by each of one or more free-pool allocator (FPA) coprocessors in the multi-chip system, a corresponding list of pools of free-buffer pointers. Based on the one or more lists of free-buffer pointers managed by the one or more FPA coprocessors, a memory allocator (MA) hardware component allocates a free buffer, associated with a chip device of the multiple chip devices, to data associated with a work item. According to at least one aspect, the data associated with the work item represents a data packet.

Claims

1. A multi-chip system comprising:

multiple chip devices, a first chip device of the multiple chip devices includes a memory allocator (MA) hardware component; and

one or more free-pool allocator (FPA) coprocessors, each associated with a corresponding chip device, and each configured to manage a corresponding list of pools of free-buffer pointers,

the MA hardware component configured to;

allocate a free buffer, associated with a chip device of the multiple chip devices, to data associated with a work item based on the one or more lists of free-buffer pointers managed by the one or more FPA coprocessors.

2. The multi-chip system as recited in claim 1, wherein the MA hardware component is further configured to maintain a list including all pools of free-buffer pointers managed by the one or more FPA coprocessors.

3. The multi-chip system as recited in claim 1, wherein a single FPA coprocessor is configured to manage a single list including all pools of free-buffer pointers associated with buffers in the multiple chip devices.

4. The multi-chip system as recited in claim 1, wherein each chip device includes a corresponding FPA coprocessor.

5. The multi-chip system as recited in claim 4, wherein for each FPA coprocessor, the free-buffer pointers, in the corresponding list of pools, point to buffers residing in the same chip device as the FPA coprocessor.

6. The multi-chip system as recited in claim 1, wherein in allocating a free buffer to the data associated with the work item, the MA hardware component is further configured to:

send a request for a free-buffer pointer to a FPA coprocessor of the one or more FPA coprocessors;

receive a response including the free-buffer pointer; and

cause the data associated with the work item to be stored in a buffer pointed to by the free-buffer pointer received.

7. The multi-chip system as recited in claim 6, wherein the free buffer allocated is freed upon the free-buffer pointer returned to the FPA coprocessor.

8. The multi-chip system as recited in claim 6, wherein the FPA coprocessor of the one or more coprocessors resides in a second chip device, of the multiple chip devices, distinct from the first chip device.

9. The multi-chip system as recited in claim 8, wherein the request for the free-buffer pointer and the response including the free-buffer pointer are exchanged between the first and second chip devices through communication channels designated for cross-chip communications between coprocessors.

10. The multi-chip system as recited in claim 1, wherein the work item is assigned to a second chip device, of the multiple chip device, for processing.

11. The multi-chip system as recited in claim 10, wherein the MA hardware component is further configured to allocate a free buffer, residing in the second chip device, to the data associated with the work item.

12. The multi-chip system as recited in claim 1, wherein the data associated with the work item represents a data packet.

13. The multi-chip system as recited in claim 1, wherein the MA hardware component includes a core processor or a coprocessor.

14. A method of memory allocation in a multi-chip system including multiple chip devices, the method comprising:

managing, by each of one or more free-pool allocator (FPA) coprocessors in the multi-chip system, a corresponding list of pools of free-buffer pointers; and

allocating, by a memory allocator (MA) hardware component, a free buffer, associated with a chip device of the multiple chip devices, to data associated with the work item based on the one or more lists of free-buffer pointers managed by the one or more FPA coprocessors.

15. The method as recited in claim 14 further comprising maintaining, by the MA hardware component, a list including all pools of free-buffer pointers managed by the one or more FPA coprocessors.

16. The method as recited in claim 14, wherein a single FPA coprocessor, in the multi-chip system, is managing a single list including all pools of free-buffer pointers associated with buffers in the multiple chip devices.

17. The method as recited in claim 14, wherein each chip device includes a corresponding FPA coprocessor.

18. The method as recited in claim 17, wherein for each FPA coprocessor, the free-buffer pointers, in the corresponding list of pools, point to buffers residing in the same chip device as the FPA coprocessor.

19. The method as recited in claim 14, wherein allocating a free buffer to the data associated with the work item includes:

sending a request, by the MA hardware component, for a free-buffer pointer to a FPA coprocessor of the one or more FPA coprocessors;

receiving, by the MA hardware component, a response including the free-buffer pointer; and

causing, by the MA hardware component, the data associated with the work item to be stored in a buffer pointed to by the free-buffer pointer received.

20. The method as recited in claim 19, wherein the free buffer allocated is freed upon the free-buffer pointer returned to the FPA coprocessor.

21. The method as recited in claim 19, wherein the FPA coprocessor of the one or more coprocessors resides in a second chip device, of the multiple chip devices, distinct from the first chip device.

22. The method system as recited in claim 21, wherein the request for the free-buffer pointer and the response including the free-buffer pointer are exchanged between the first and second chip devices through communication channels designated for cross-chip communications between coprocessors.

23. The method as recited in claim 14, wherein the work item is assigned to a second chip device, of the multiple chip device, for processing.

24. The method as recited in claim 23, wherein allocating a free buffer includes allocating a free buffer, residing in the second chip device, to the data associated with the work item.

25. The method as recited in claim 14, wherein the data associated with the work item represents a data packet.

26. The method as recited in claim 14, wherein the MA hardware component includes a core processor or a coprocessor.