Apparatus for configuring partitions within phase change memory of tablet computer with integrated memory controller emulating mass storage to storage driver based on request from software

• US 9,529,708 B2
• Filed: 09/30/2011
• Issued: 12/27/2016
• Est. Priority Date: 09/30/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Puthiyedath, Leena K., Fanning, Blaise, Opferman, Toby, Crossland, James B.
• Primary Examiner(s): PEYTON, TAMMARA R
• Application Number:
  US13/976,362
• Publication Number:
  US 20140297938A1
• Time in Patent Office: 1,915 Days
• Field of Search: 710/1, 710 8- 10, 711/103, 711/114
• US Class Current: 1/1
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/1004 Compatibility, e.g. with legacy hardware
• CPC Class Codes: G06F 2212/1056 Simplification
• CPC Class Codes: G06F 2212/2024 Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/251 Local memory within processor subsystem
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0643 Management of files
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.

Claims

1. An apparatus comprising:

a

processor to execute software;

a non flash non-volatile memory coupled to the processor, the non flash non-volatile memory comprising a non flash non-volatile random access memory portion that is byte-rewritable and byte-erasable by the processor, the non flash non-volatile random access memory portion to act as a system memory for the processor'"'"'s software to execute instructions out of, the non flash non-volatile memory also comprising a partition that is exposed to the software as mass storage;

a memory controller coupled between the processor and the non flash non-volatile memory to access the non flash non-volatile random access system memory portion, the memory controller also to perform a memory access operation to access the partition in response to a request from the software for access to a mass storage wherein the memory controller is to emulate the mass storage to a storage driver in response to the request from the software.

2. The apparatus of claim 1, wherein the non flash non-volatile memory comprises phase change memory (PCM).

3. The apparatus of claim 1, wherein the non flash non-volatile memory comprises chalcogenide.

4. The apparatus of claim 1, wherein the partition is configured as a random access memory (RAM) disk.

5. The apparatus of claim 1, wherein the partition is to store a file system that contains a file, which is mapped to a virtual address space of an application executed by the processor, such that access to the file incurs no page fault.

6. The apparatus of claim 1, wherein the processor is to execute an application that performs memory operations to allocate and access an address space of the non flash non-volatile memory.

7. A method comprising:

receiving, by a memory controller, a request from software executed by a processor to access mass storage, the request not being directed to a peripheral controller; and

performing, by the memory controller, a memory access operation in response to the request to access a partition of non flash non-volatile random access memory that is exposed to the software as mass storage, the memory controller also emulating the mass storage to a storage driver in response to the request from the software;

executing the software by calling instructions and data from another portion of the non flash non volatile memory that behaves as a byte rewritable and byte erasable system memory.

8. The method of claim 7, wherein the non flash non-volatile random access memory comprises phase change memory (PCM).

9. The method of claim 7, wherein the non flash non-volatile memory comprises chalcogenide.

10. A system comprising:

a processor to execute software;

a memory controller coupled to the processor, the memory controller to access a system memory, a first portion of the system memory comprising a dynamic random access memory (DRAM) and a second portion of the system memory comprising a first partition of a non flash non-volatile random access memory that is byte-rewritable and byte-erasable by the processor, the first and second portions of the system memory for the software to execute instructions out of, the memory controller also to couple to a second partition of the non flash non-volatile random access memory and to perform a memory access operation to access the second partition of the non flash non-volatile random access memory in response to a request from the software for access to a mass storage, the memory controller also to emulate the mass storage to a storage driver in response to the request from the software.

11. The system of claim 10, wherein the non flash non-volatile random access system memory comprises phase change memory (PCM).

12. The system of claim 10, wherein the non flash non-volatile random access system memory comprises chalcogenide.

13. The system of claim 10, wherein the second partition of the non flash non-volatile random access memory is configured as a random access memory (RAM) disk.

14. The system of claim 10, wherein the second partition of the non flash non-volatile random access system memory is to store a file system that contains a file, which is mapped to a virtual address space of an application executed by the processor, such that access to the file incurs no page fault.

15. The system of claim 10, wherein the processor is to execute an application that performs memory operations to allocate and access an address space of the system memory.