Techniques for balancing accesses to memory having different memory types

• US 9,529,712 B2
• Filed: 07/26/2011
• Issued: 12/27/2016
• Est. Priority Date: 07/26/2011
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Kelleher, Brian, Kilgariff, Emmett M., Yamamoto, Wayne
• Primary Examiner(s): Chery, Mardochee
• Assistant Examiner(s): Doan, Khoa D
• Application Number:
  US13/191,438
• Publication Number:
  US 20130031328A1
• Time in Patent Office: 1,981 Days
• Field of Search: 711/202
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments of the present technology are directed toward techniques for balancing memory accesses to different memory types.

Claims

1. A method comprising:

determining one or more parameters, including a data access rate, of a plurality of different types of memory devices coupled to a computing device;

and configuring a memory mapping algorithm to balance traffic to two or more memory devices of different types together for a given memory access as a function of the one or more determined parameters including the data access rates of the two or more memory devices of different types and to stripe memory accesses for a first location in an address space across the two or more memory devices of different types in a ratio of the data access rate of the two or more memory devices of different types.

2. The method according to claim 1, further comprising configuring the memory mapping algorithm to dynamically access memories of one or more types as a function of one or more other determined parameters.

3. The method according to claim 1, further comprising:

determining one or more parameters of the computing device or load on the computing device; and

configuring the memory mapping algorithm to dynamically access memory of one or more types as a function of one or more determined parameters of the computing device or load on the computing device.

4. The method according to claim 1, further comprising:

organizing each memory device into one or more partitions as a function of the one or more determined parameters including the data rate of the memory devices;

and configuring the memory mapping algorithm to balance traffic to partitions in the two or more memory devices of two or more different types together for the given memory access as a function of the one or more determined parameters including the data rate of the memory devices.

5. The method according to claim 1, wherein the memory mapping is configured to access a leftover portion, after striping, of a first or second of the two or more memory devices, wherein the leftover portion of the first or second of the two or more memory devices is accessed, at a second location in the address space, as contiguous memory and not striped memory.

6. A method comprising:

receiving a memory access request at a given physical address and a given length;

Determining locations in a plurality of memory devices for the given physical address and the given length from a mapping, wherein the mapping balances traffic between two or more memories of different memory types together for the memory access request as a function of one or more parameters including a data access rate of the different memory types and stripes memory accesses for a first location in an address space across the two or more memory devices of different types in a ratio of the data access rate, of the two or more memory device of different types;

And accessing the locations in the corresponding memory device.

7. The method according to claim 6, wherein the mapping further balances traffic between partitions in the two or more memories of different types together for the memory access request as a function of one or more parameters including a data rate of the different memory types.

8. The method according to claim 6, wherein the plurality of memory devices comprises a first set of memory devices operating at first data rate and a second set of memory devices operating at a second data rate.

9. The method according to claim 8, wherein the locations for write memory accesses are dynamically mapped to memories of one or more types as a function of one or more other parameters for another memory access request instead of balanced as a function of the data rate of the different memory types.

10. The method according to claim 9, wherein the one or more other parameters include a memory access traffic load parameter.

11. The method according to claim 9, wherein the one or more other parameters include a memory power consumption parameter.

12. A method comprising:

an initialization phase including;

determining one or more parameters, including a data rate, of a plurality of memory devices including memory devices of two or more different types coupled to a computing device; and

configuring a memory mapping algorithm to balance traffic between memory devices of first and second types together for a give memory access as a function of the one or more determined parameters including the data rate of the memory devices of the first and second types and to stripe memory accesses across the memory devices of the first and second types in a ratio of the data rates of the first and second types; and

an operating phase including;

receiving a memory access request at a given physical address and a given length;

determining location in one or more of the memory devices for the given physical address and the given length based on the memory mapping algorithm; and

accessing the locations in the one or more memory devices.

13. The method according to claim 12, wherein memory of the first type is characterized by a first data rate, and memory of the second type is characterized by a second data rate that is faster than the first data rate.

14. The method according to claim 13, wherein memory of the first type is characterized by a first storage capacity, and memory of the second type is characterized by a second storage capacity that is less than the first storage capacity.

15. The method according to claim 14, wherein memory of the first type is characterized by a first power rate, and memory of the second type is characterized by a second power rate that is greater than the first power rate.

16. The method according to claim 15, wherein memory of the first type is characterized by a first cost, and memory of the second type is characterized by a second cost that is greater than the first cost.

17. The method according to claim 12, wherein the configured memory mapping algorithm dynamically accesses memory of the first type if a memory access traffic load parameter is in a predetermined range, instead of balancing traffic between memory of the first and second types.

18. The method according to claim 12, wherein the configured memory mapping algorithm dynamically accesses memory of the first type if a power consumption parameter is in a predetermined range, instead of balancing traffic between memory of the first and second types.