Optimizing write and wear performance for a memory

• US 9,529,716 B2
• Filed: 10/18/2013
• Issued: 12/27/2016
• Est. Priority Date: 12/16/2005
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Fortin, Michael R., Reinauer, Robert L.
• Primary Examiner(s): Wong, Titus
• Application Number:
  US14/058,078
• Publication Number:
  US 20140047189A1
• Time in Patent Office: 1,166 Days
• Field of Search: 710/29
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0873 Mapping of cache memory to specific storage devices or parts thereof
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/3042 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G06F 2212/305 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays

Abstract

Determining and using the ideal size of memory to be transferred from high speed memory to a low speed memory may result in speedier saves to the low speed memory and a longer life for the low speed memory.

Claims

1. A method performed on a computing device, the method comprising:

caching, by the computing device, data in a first memory that is volatile random access memory, where the data being cached is designated to be written to a third memory that is disk-based memory;

determining a preferred write size for the third memory; and

backing-up, by the computing device after beginning the caching but prior to completion of the caching of a preferred amount of the data in the first memory, the data being cached to a second memory that is disk-based memory or flash-based memory, where the preferred amount is based on the determined preferred write size of the third memory.

2. The method of claim 1 where the third memory is a flash memory device.

3. The method of claim 1 further comprising writing, in response to the preferred amount of the data being cached in the first memory, the preferred amount of the cached data to the third memory.

4. The method of claim 3 where the writing is further in response to a period of low system activity.

5. The method of claim 3 further comprising determining that a portion of the cached data in the first memory has been replaced with newer cached data prior to the writing.

6. The method of claim 3 further comprising determining that a portion of the cached data in the first memory is duplicate data, where at least some of the determined duplicate data is not included in the preferred amount of the cached data written to the third memory.

7. The method of claim 3 further comprising invalidating a portion of the cached data in the first memory in response to the portion being impacted by a write operation prior to the writing.

8. A computing device comprising:

at least one processor;

a first memory that is volatile random access memory;

a second memory that is disk-based memory or flash-based memory;

a third memory that is disk-memory; and

computer-executable instructions that, based on execution by the at least one processor, configured the computing device to perform actions comprising;

caching data in the first memory, where the data being cached is designated to be written to the third memory;

determining a preferred write size for the third memory; and

backing-up, after beginning the caching but prior to completion of the caching of a preferred amount of the data in the first memory by the caching, the data being cached to the second memory, where the preferred amount is based on the determined preferred write size of the third memory.

9. The computing device of claim 8 where the third memory is a flash memory device.

10. The computing device of claim 8, the actions further comprising writing, in response to the preferred amount of the data being cached in the first memory, the preferred amount of the cached data to the third memory.

11. The computing device of claim 10 where the writing is further in response to a period of low system activity.

12. The computing device of claim 10, the actions further comprising determining that a portion of the cached data in the first memory has been replaced with newer cached data prior to the writing.

13. The computing device of claim 10, the actions further comprising determining that a portion of the cached data in the first memory is duplicate data, where at least some of the determined duplicate data is not included in the preferred amount of the cached data written to the third memory.

14. The computing device of claim 10, the actions further comprising invalidating a portion of the cached data in the first memory in response to the portion being impacted by a write operation prior to the writing.

15. At least one computer storage device comprising:

memory that comprises computer-executable instructions that, based on execution by a computing device, configure the computing device to perform actions comprising;

caching data in a first memory that is volatile random access memory, where the data being cached is designated to be written to a third memory that is disk-based memory;

determining a preferred write size for the third memory; and

backing-up, after beginning the caching but prior to completion of the caching of a preferred amount of the data in the first memory, the data being cached, to a second memory, where the preferred amount is based on the determined preferred write size of the third memory.

16. The at least one computer storage device of claim 15, the actions further comprising writing, in response to the preferred amount of the data being cached in the first memory, the preferred amount of the cached data to the third memory.

17. The at least one computer storage device of claim 16 where the writing is further in response to a period of low system activity.

18. The at least one computer storage device of claim 16, the actions further comprising determining that a portion of the cached data in the first memory has been replaced with newer cached data prior to the writing.

19. The at least one computer storage device of claim 16, the actions further comprising determining that a portion of the cached data in the first memory is duplicate data, where at least some of the determined duplicate data is not included in the preferred amount of the cached data written to the third memory.

20. The at least one computer storage device of claim 16, the actions further comprising invalidating a portion of the cached data in the first memory in response to the portion being impacted by a write operation prior to the writing.