Layered architecture for hybrid controller
First Claim
1. A controller comprising at least one hardware processor for a hybrid memory comprising a main memory and a cache for the main memory, the controller comprising a hierarchy of abstraction layers each abstraction layer configured to provide at least one component of a cache management structure, each pair of abstraction layers comprising processors communicating through an application programming interface (API), the controller configured to receive incoming memory access requests from a host processor and to manage outgoing memory access requests routed to the cache using the plurality of abstraction layers,wherein at least one of the abstraction layers is configured to:
- receive the incoming memory access requests from the host processor, the incoming memory access requests including a range of host logical block addresses (LBAs);
route the incoming memory access requests to a set of incoming queues by implementing a priority scheme, the set of incoming queues comprising an incoming execute queue, the priority scheme comprising;
routing invalidate requests in the invalidate ready queue to the execute queue as a highest priority;
routing read requests in the read ready queue to the execute queue as a second highest priority; and
routing promotion requests in the promotion ready queue as a third highest priority;
map the range of host LBAs into clusters of cache LBAs;
transform each incoming memory access request into one or more outgoing memory access requests, each outgoing memory access request including a range or cluster of cache LBAs;
route the outgoing memory access requests from the set of incoming queues into a set of outgoing queues, the outgoing queues comprising;
a set of outgoing execute queues, wherein each entry in the incoming execute queue is associated with a plurality of entries in an outgoing execute queue, andan outgoing free queue containing a number outgoing nodes, wherein an outgoing node is removed from the outgoing free queue when an outgoing memory access request is queued in one of the outgoing execute queues and the outgoing node is returned to the outgoing free queue; and
access the cache using the outgoing memory access requests.
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Abstract
Approaches for implementing a controller for a hybrid memory that includes a main memory and a cache for the main memory are discussed. The controller comprises a hierarchy of abstraction layers, wherein each abstraction layer is configured to provide at least one component of a cache management structure. Each pair of abstraction layers utilizes processors communicating through an application programming interface (API). The controller is configured to receive incoming memory access requests from a host processor and to manage outgoing memory access requests routed to the cache using the plurality of abstraction layers.
90 Citations
10 Claims
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1. A controller comprising at least one hardware processor for a hybrid memory comprising a main memory and a cache for the main memory, the controller comprising a hierarchy of abstraction layers each abstraction layer configured to provide at least one component of a cache management structure, each pair of abstraction layers comprising processors communicating through an application programming interface (API), the controller configured to receive incoming memory access requests from a host processor and to manage outgoing memory access requests routed to the cache using the plurality of abstraction layers,
wherein at least one of the abstraction layers is configured to: -
receive the incoming memory access requests from the host processor, the incoming memory access requests including a range of host logical block addresses (LBAs); route the incoming memory access requests to a set of incoming queues by implementing a priority scheme, the set of incoming queues comprising an incoming execute queue, the priority scheme comprising; routing invalidate requests in the invalidate ready queue to the execute queue as a highest priority; routing read requests in the read ready queue to the execute queue as a second highest priority; and routing promotion requests in the promotion ready queue as a third highest priority; map the range of host LBAs into clusters of cache LBAs; transform each incoming memory access request into one or more outgoing memory access requests, each outgoing memory access request including a range or cluster of cache LBAs; route the outgoing memory access requests from the set of incoming queues into a set of outgoing queues, the outgoing queues comprising; a set of outgoing execute queues, wherein each entry in the incoming execute queue is associated with a plurality of entries in an outgoing execute queue, and an outgoing free queue containing a number outgoing nodes, wherein an outgoing node is removed from the outgoing free queue when an outgoing memory access request is queued in one of the outgoing execute queues and the outgoing node is returned to the outgoing free queue; and access the cache using the outgoing memory access requests. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of controlling a hybrid memory comprising a main memory and a cache for the main memory, the method comprising:
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receiving incoming memory access requests from a host processor in a first abstraction layer of a hybrid memory controller, each memory access request including a range of host logical block addresses (LBAs); implementing a first component of a cache management protocol in the first abstraction layer; routing incoming memory access requests to a second abstraction layer, the first and second abstraction layers communicating through a software interface; in the second abstraction layer, implementing a second component of the cache management protocol; mapping the range of host LBAs to cache LBAs in the second abstraction layer; transforming the incoming memory access requests to outgoing memory access requests that include the cache LBAs, wherein at least one of the abstraction layers is configured to; receive the incoming memory access requests from the host processor, the incoming memory access requests including a range of host logical block addresses (LBAs); route the incoming memory access requests to a set of incoming queues by implementing a priority scheme, the set of incoming queues comprising an incoming execute queue, the priority scheme comprising; routing invalidate requests in the invalidate ready queue to the execute queue as a first highest priority; routing read requests in the read ready queue to the execute queue as a second highest priority; and routing promotion requests in the promotion ready queue as a third highest priority; and accessing the cache using the outgoing memory access requests.
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Specification