Layered architecture for hybrid controller

• US 9,529,724 B2
• Filed: 07/06/2012
• Issued: 12/27/2016
• Est. Priority Date: 07/06/2012
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Jannyavula Venkata, Sumanth, Sawin, James David, Yulizar, Yunaldi, Goss, Ryan James
• Primary Examiner(s): Thammavong, Prasith
• Assistant Examiner(s): Tsang, Kenneth
• Application Number:
  US13/543,303
• Publication Number:
  US 20140013027A1
• Time in Patent Office: 1,635 Days
• Field of Search: 711/103
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems

Abstract

Approaches for implementing a controller for a hybrid memory that includes a main memory and a cache for the main memory are discussed. The controller comprises a hierarchy of abstraction layers, wherein each abstraction layer is configured to provide at least one component of a cache management structure. Each pair of abstraction layers utilizes processors communicating through an application programming interface (API). The controller is configured to receive incoming memory access requests from a host processor and to manage outgoing memory access requests routed to the cache using the plurality of abstraction layers.

Claims

1. A controller comprising at least one hardware processor for a hybrid memory comprising a main memory and a cache for the main memory, the controller comprising a hierarchy of abstraction layers each abstraction layer configured to provide at least one component of a cache management structure, each pair of abstraction layers comprising processors communicating through an application programming interface (API), the controller configured to receive incoming memory access requests from a host processor and to manage outgoing memory access requests routed to the cache using the plurality of abstraction layers,

wherein at least one of the abstraction layers is configured to:

receive the incoming memory access requests from the host processor, the incoming memory access requests including a range of host logical block addresses (LBAs);

route the incoming memory access requests to a set of incoming queues by implementing a priority scheme, the set of incoming queues comprising an incoming execute queue, the priority scheme comprising;

routing invalidate requests in the invalidate ready queue to the execute queue as a highest priority;

routing read requests in the read ready queue to the execute queue as a second highest priority; and

routing promotion requests in the promotion ready queue as a third highest priority;

map the range of host LBAs into clusters of cache LBAs;

transform each incoming memory access request into one or more outgoing memory access requests, each outgoing memory access request including a range or cluster of cache LBAs;

route the outgoing memory access requests from the set of incoming queues into a set of outgoing queues, the outgoing queues comprising;

a set of outgoing execute queues, wherein each entry in the incoming execute queue is associated with a plurality of entries in an outgoing execute queue, and

an outgoing free queue containing a number outgoing nodes, wherein an outgoing node is removed from the outgoing free queue when an outgoing memory access request is queued in one of the outgoing execute queues and the outgoing node is returned to the outgoing free queue; and

access the cache using the outgoing memory access requests.

2. The controller of claim 1, wherein the main memory comprises a magnetic disk memory and the cache comprises flash memory.

3. The controller of claim 1, wherein the plurality of abstraction layers comprises first, second, and third abstraction layers.

4. The controller of claim 3, wherein:

the main memory comprises a memory space that corresponds to host logical block addresses (LBAs);

the first abstraction layer is configured to issue to the second abstraction layer memory access requests that include a host LBA range; and

the second abstraction layer is configured map the host LBA range received from the first abstraction layer to one or more clusters of cache LBAs and to issue to the third abstraction layer memory access requests that include the cache LBA clusters.

5. The controller of claim 4, wherein:

the plurality of abstraction layers comprises a fourth abstraction layer; and

the third abstraction layer is configured to map the clusters of cache LBAs to die, block, and page locations and to issue to the fourth abstraction layer memory access requests that include the die, block, and page locations.

6. The controller of claim 1, wherein:

the main memory comprises a memory space that corresponds to host logical block addresses (LBAs);

at least one of the abstraction layers comprises;

a history tracking module configured to track host read operations affecting a first host LBA;

an analysis module coupled to the history tracking module and configured to determine one or more criteria associated with the host read operations, the criteria being indicative of future read requests of second host LBA associated with the first host LBA; and

a caching module coupled to the analysis module and configured to cause data of the at least the second host LBA from the main memory to be copied to the cache if the criteria meets a threshold.

7. The controller of claim 1, wherein at least one of the abstraction layers comprises:

a speculative read module configured to define a speculative address range proximate to a request address range associated with a host read request affecting the main memory, wherein speculative data stored in the speculative address range is not requested via the host read request;

an analysis module configured to determine a criterion indicative of future read requests of associated with the speculative data; and

a caching module coupled to the speculative read module and configured to copy the speculative data from the main memory to the cache, the cache including at least one of a primary cache and a secondary cache, together with data of the host read request in response to the criterion meeting a threshold, the primary cache and the secondary cache mirroring respective portions of the main memory.

8. The controller of claim 1, wherein the cache comprises a primary cache and a secondary cache, and at least one of the abstraction layers is configured to

cause a new segment of data to be copied to the primary cache mirroring a first portion of the main memory, the new segment of data copied in response to a read request from a host;

determine a criterion for copying data from the primary cache to the secondary cache, the secondary cache mirroring a second portion of the main memory, wherein the criterion gives higher priority to segments having addresses not yet selected for reading by the host; and

in response to the new segment of data being copied into the secondary cache, copy a selected segment of data from the primary cache to the secondary cache in response to the selected segment satisfying the criterion.

9. The controller of claim 1, wherein:

the main memory comprises a memory space that corresponds to logical block addresses (LBAs) of the host processor; and

at least one of the abstraction layers is configured to map clusters of host LBAs to clusters of cache LBAs, the cache LBAs corresponding to a memory space of the cache, the mapping of the host LBA clusters to the cache LBA clusters being fully associative wherein any host LBA cluster can be mapped to any cache LBA cluster.

10. A method of controlling a hybrid memory comprising a main memory and a cache for the main memory, the method comprising:

receiving incoming memory access requests from a host processor in a first abstraction layer of a hybrid memory controller, each memory access request including a range of host logical block addresses (LBAs);

implementing a first component of a cache management protocol in the first abstraction layer;

routing incoming memory access requests to a second abstraction layer, the first and second abstraction layers communicating through a software interface;

in the second abstraction layer, implementing a second component of the cache management protocol;

mapping the range of host LBAs to cache LBAs in the second abstraction layer;

transforming the incoming memory access requests to outgoing memory access requests that include the cache LBAs, wherein at least one of the abstraction layers is configured to;

receive the incoming memory access requests from the host processor, the incoming memory access requests including a range of host logical block addresses (LBAs);

route the incoming memory access requests to a set of incoming queues by implementing a priority scheme, the set of incoming queues comprising an incoming execute queue, the priority scheme comprising;

routing invalidate requests in the invalidate ready queue to the execute queue as a first highest priority;

routing read requests in the read ready queue to the execute queue as a second highest priority; and

routing promotion requests in the promotion ready queue as a third highest priority; and

accessing the cache using the outgoing memory access requests.