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Computer system including CPU or peripheral bridge directly connected to a low voltage differential signal channel that communicates serial bits of a peripheral component interconnect bus transaction in opposite directions

DC CAFC
  • US 9,529,768 B2
  • Filed: 03/13/2014
  • Issued: 12/27/2016
  • Est. Priority Date: 05/14/1999
  • Status: Expired due to Term
First Claim
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1. A computer, comprising:

  • an integrated central processing unit, interface controller and Phase-Locked Loop (PLL) clock circuitry in a single chip,a Low Voltage Differential Signal (LVDS) channel directly extending from the interface controller to convey address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in a serial form, wherein the first LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction; and

    wherein the PLL clock circuitry generates different clock frequencies, and the interface controller conveys the PCI bus transaction through the LVDS channel based on the different clock frequencies.

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