Computer system including CPU or peripheral bridge directly connected to a low voltage differential signal channel that communicates serial bits of a peripheral component interconnect bus transaction in opposite directions

• US 9,529,768 B2
• Filed: 03/13/2014
• Issued: 12/27/2016
• Est. Priority Date: 05/14/1999
• Status: Expired due to Term

• Current Assignee: Acqis LLC (Acqis Technology, Inc.)
• Original Assignee: Acqis LLC (Acqis Technology, Inc.)
• Inventors: Chu, William W. Y.
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US14/209,922
• Publication Number:
  US 20140195713A1
• Time in Patent Office: 1,020 Days
• Field of Search: 710305-317, 710104-110, 710 62- 64, 710 72- 74
• US Class Current: 1/1
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.

Claims

1. A computer, comprising:

an integrated central processing unit, interface controller and Phase-Locked Loop (PLL) clock circuitry in a single chip,

a Low Voltage Differential Signal (LVDS) channel directly extending from the interface controller to convey address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in a serial form, wherein the first LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction; and

wherein the PLL clock circuitry generates different clock frequencies, and the interface controller conveys the PCI bus transaction through the LVDS channel based on the different clock frequencies.

2. The computer of claim 1 wherein the interface controller conveys the PCI bus transaction through the LVDS channel based on a selected frequency of the different clock frequencies.

3. The computer of claim 1 wherein the interface controller is configurable to convey the PCI bus transaction with different serialized forms through the LVDS channel on different numbers of differential signal pairs.

4. A computer, comprising:

a central processing unit;

an integrated peripheral bridge, interface controller, and Phase-Locked Loop (PLL) clock circuitry in a single chip, directly coupled to the central processing unit without any intervening PCI bus;

a low voltage differential signal (LVDS) channel directly extending from the interface controller comprising at least two serial channels of unidirectional, differential signal pairs to convey data in opposite directions, wherein the LVDS channel conveys encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form; and

wherein the PLL clock circuitry generates different clock frequencies, and the interface controller conveys the PCI bus transaction through the LVDS channel based on the different clock frequencies.

5. The computer of claim 4 wherein the interface controller conveys the PCI bus transaction with different data rate frequencies through the LVDS channel based on the different clock frequencies.

6. The computer of claim 4 wherein the interface controller is configurable to convey the PCI bus transaction with different serialized forms through the LVDS channel on different numbers of differential signal pairs.

7. A printed circuit board, comprising:

a central processing unit connected directly to a first Low Voltage Differential Signal (LVDS) channel to convey encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form, wherein the LVDS channel comprises four or more unidirectional, differential signal line pairs to convey data in a first direction, and four or more unidirectional, differential signal line pairs to convey data in a second, opposite direction,

an interface controller comprising Phased-Locked Loop (PLL) clock circuitry, coupled to a second Low Voltage Differential Signal (LVDS) channel with two sets of unidirectional, differential signal line pairs to convey serial data in opposite direction, and

a socket for a system memory module directly coupled to the central processing unit.

8. The printed circuit board of claim 7, wherein the interface controller is configurable to convey encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction with different serialized forms, through the second LVDS channel on different numbers of differential signal pairs.

9. The printed circuit board of claim 7, wherein the PLL clock circuitry generates different clock frequencies;

and wherein the interface controller generates a data transfer frequency based on one of the different clock frequencies, to convey encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction through the second LVDS channel.

10. A printed circuit board, comprising:

a central processing unit;

a peripheral bridge directly coupled to the central processing unit without any intervening Peripheral Component Interconnect (PCI) bus;

a low voltage differential signal (LVDS) channel directly extending from the peripheral bridge comprising two unidirectional, serial channels of multiple differential signal line pairs to convey data in opposite directions, wherein the LVDS channel conveys address and data bits of a PCI bus transaction in serial form; and

a network controller coupled to the central processing unit.

11. The printed circuit board of claim 10 wherein the peripheral bridge comprises an interface controller directly coupled to the LVDS channel, wherein the interface controller is configurable to convey the PCI bus transaction through the LVDS channel with different serialized forms on different numbers of differential signal pairs.

12. The printed circuit board of claim 11 wherein the interface controller couples to Phased-Locked Loop (PLL) clock circuitry, and wherein the interface controller generates different data transfer frequencies based on different frequencies generated by the PLL clock circuitry, to convey the PCI bus transaction through the LVDS channel.

13. A computer, comprising:

an integrated central processing unit and interface controller in a single chip;

a first Low Voltage Differential Signal (LVDS) channel directly extending from the interface controller to convey address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in a serial bit stream, wherein the first LVDS channel comprises first unidirectional, multiple, differential signal pairs to convey data in a first direction and second unidirectional, multiple, differential signal pairs to convey data in a second, opposite direction; and

a system memory directly coupled to the integrated central processing unit and interface controller.

14. The computer of claim 13, wherein the interface controller is configurable to convey the PCI bus transaction through the LVDS channel on different numbers of differential signal pairs.

15. The computer of claim 13, further comprising a connector adapted to convey a serial bit stream of address and data bits of a PCI bus transaction through a second Low Voltage Differential Signal (LVDS) channel comprising two unidirectional, differential signal pairs that transmit data in opposite directions.

16. The computer of claim 15, wherein the second LVDS channel is configurable in different numbers of differential signal pairs to transmit the PCI bus transaction.

17. The computer of claim 13, wherein the interface controller couples to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller generates a data transfer signal to convey the PCI bus transaction through the LVDS channel based on one of the different clock frequencies generated by the PLL clock circuitry.

18. A computer system, comprising:

a computer with

a connector configurable for coupling to a console;

an integrated central processing unit, graphics subsystem and interface controller in a single chip;

a first Low Voltage Differential Signal (LVDS) channel directly coupled to the interface controller, adapted to convey encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form, wherein the first LVDS channel comprises a first plurality of unidirectional, differential signal pairs to convey data in a first direction and a second plurality of unidirectional, differential signal pairs to convey data in a second, opposite direction;

wherein the integrated graphics subsystem directly outputs digital video display signals in a third differential signal channel; and

wherein the integrated interface controller is configurable to convey the PCI bus transaction on different numbers of differential signal pairs.

19. The computer system of claim 18, wherein the interface controller couples to Phased-Locked Loop (PLL) clock circuitry, and wherein the interface controller generates a first data transfer signal to convey the PCI bus transaction through the LVDS channel based on one of the different clock frequencies generated by the PLL clock circuitry.

20. The computer system of claim 19, wherein the interface controller generates a second data transfer signal to convey the PCI bus transaction through the LVDS channel based on another one of the different clock frequencies generated by the PLL clock circuitry.

21. The computer system of claim 18, wherein the interface controller is configurable to convey the PCI bus transaction through the first LVDS channel on different numbers of differential signal pairs.

22. A computer, comprising:

an integrated central processing unit, graphics subsystem and interface controller in a single chip, wherein the integrated interface controller is directly coupled to a first Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, multiple serial bit channels communicating encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in opposite directions;

a connector adapted to convey digital video display signals from a differential signal channel directly connected to the integrated graphics subsystem, and a serial bit stream of encoded address and data bits of a PCI bus transaction in a second LVDS channel comprising unidirectional, differential signal pairs; and

wherein the computer couples to a console through the connector.

23. The computer of claim 22, wherein the interface controller is configurable to couple to different numbers of serial bit channels to convey the PCI bus transaction through the LVDS channel.

24. The computer system of claim 22, wherein the second LVDS channel is configurable in different numbers of differential signal pairs to transmit the PCI bus transaction.

25. The computer of claim 22, wherein the integrated interface controller couples to Phase-Locked Loop (PLL) clock circuitry in the single chip, and wherein the interface controller generates different data transfer frequencies to convey the PCI bus transaction through the LVDS channel based on different clock frequencies generated by the PLL clock circuitry.

26. The computer of claim 22, wherein the differential signal channel uses Transition Minimized Differential Signaling (TMDS) to convey digital video display signals.

27. A computer comprising

an integrated central processing unit and graphics subsystem in a single chip directly coupled to a first Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, multiple serial bit channels transmitting encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in opposite directions;

an interface controller directly coupled to a second LVDS channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions;

a connector coupled to the interface controller adapted to convey a serial bit stream of encoded address and data bits of a PCI bus transaction from the second LVDS channel; and

a console, wherein the computer is adapted to couple to the console through the connector.

28. The computer of claim 27, wherein the interface controller is configurable to couple to different numbers of serial bit channels to convey the PCI bus transaction to the connector through the second LVDS channel.

29. The computer of claim 27, wherein the first LVDS channel is adaptable to different data transfer frequencies to convey the PCI bus transaction.

30. A modular system, comprising:

a computer comprising;

a central processing unit directly connected to a first Low Voltage Differential Signal (LVDS) channel comprising two sets of four or more, unidirectional, differential signal pairs transmitting data packets serially in opposite directions, wherein the data packets communicate encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form,

a system memory directly connected to the central processing unit, and

a connector adapted to convey digital video display signals and to transmit a serial bit stream of encoded address and data bits of a PCI bus transaction through a second LVDS channel comprising two sets of unidirectional, differential signal pairs in opposite direction; and

a console, wherein the computer is adapted to couple to the console through the connector.

31. The modular computer of claim 30, wherein the first LVDS channel is adaptable to different data transfer frequencies to convey the PCI bus transaction.

32. The modular computer of claim 30, wherein the second LVDS channel is configurable in different numbers of differential signal pairs to convey the PCI bus transaction.

33. A computer, comprising:

a central processing unit comprising an interface controller directly connected to a first Low Voltage Differential Signal (LVDS) channel comprising at least two sets of unidirectional, multiple, differential signal pairs transmitting encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in opposite directions, wherein the interface controller is configured to convey the PCI bus transaction through the LVDS channel in different numbers of differential signal pairs;

a system memory directly connected to the central processing unit;

a mass storage device coupled to the central processing unit; and

a second Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, differential signal pairs transmitting data serially in opposite directions, wherein the second LVDS channel is a point-to-point data communication link.

34. The computer of claim 33, wherein the computer couples to a console and wherein the central processing unit communicates to the console through the second LVDS channel utilizing a Universal Serial Bus (USB) protocol.

35. The computer of claim 33, wherein the interface controller comprises Phased-Locked Loop (PLL) clock circuitry, and wherein the interface controller generates a data transfer signal to convey the PCI bus transaction through the first LVDS channel based on one of the different clock frequencies generated by the PLL clock circuitry.

36. A computer, comprising:

an integrated central processing unit and graphics subsystem in a single chip;

a first Low Voltage Differential Signal (LVDS) channel directly extending from the integrated central processing unit and graphics subsystem, wherein the first LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction, wherein the first LVDS channel conveys data using a Universal Serial Bus (USB) protocol;

a system memory directly coupled to the integrated central processing unit and graphics subsystem; and

a graphics memory directly coupled to the integrated central processing unit and graphics subsystem.

37. The computer of claim 36, further comprising a connector adapted to convey encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction through a second LVDS channel comprising two unidirectional, differential signal pairs that transmit data in opposite directions.

38. The computer of claim 37, wherein the second LVDS channel is configurable to convey the PCI bus transaction on different numbers of differential signal pairs.

39. A computer, comprising:

an integrated central processing unit and interface controller in a single chip;

a Low Voltage Differential Signal (LVDS) channel directly extending from the integrated central processing unit and interface controller to convey encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in a serial form, wherein the LVDS channel comprises a first unidirectional, multiple, differential signal line pairs to convey data in a first direction and a second unidirectional, multiple, differential signal line pairs to convey data in a second, opposite direction;

a socket for a system memory module, directly coupled to the integrated central processing unit and interface controller; and

wherein the interface controller is configurable to convey the PCI bus transaction through the LVDS channel on different numbers of differential signal line pairs.

40. The computer of claim 39, further comprising a second Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, differential signal pairs transmitting data serially in opposite directions to convey data using a Universal Serial Bus (USB) protocol.