Computer system including CPU or peripheral bridge directly connected to a low voltage differential signal channel that communicates serial bits of a peripheral component interconnect bus transaction in opposite directions

• US 9,529,769 B2
• Filed: 02/26/2016
• Issued: 12/27/2016
• Est. Priority Date: 05/14/1999
• Status: Active Grant

• Current Assignee: Acqis LLC (Acqis Technology, Inc.)
• Original Assignee: Acqis LLC (Acqis Technology, Inc.)
• Inventors: Chu, William W. Y.
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US15/055,436
• Publication Number:
  US 20160179744A1
• Time in Patent Office: 305 Days
• Field of Search: 710305-317, 710104-110, 710 62- 64, 710 72- 74
• US Class Current: 1/1
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer system has a computer with an integrated central processing unit and graphics subsystem in a single chip. The graphics subsystem directly couples to a unidirectional differential signal channel to output digital video data. A connector is configurable for external peripheral communication. A first Low Voltage Differential Signal (LVDS) channel directly couples to the connector. The first LVDS channel has two unidirectional, differential signal pairs transmitting data in opposite directions to convey Universal Serial Bus (USB) protocol data for external peripheral communication. The unidirectional different signal channel conveys Transition Minimized Differential Signaling (TMDS) signals as digital video data.

Claims

1. A computer system, comprising:

a computer with

an integrated central processing unit and graphics subsystem in a single chip;

wherein the graphics subsystem directly couples to a unidirectional differential signal channel to output digital video data; and

a connector configurable for external peripheral communication;

a first Low Voltage Differential Signal (LVDS) channel directly coupled to the connector, comprising two unidirectional, differential signal pairs transmitting data in opposite directions to convey Universal Serial Bus (USB) protocol data for external peripheral communication, and

wherein the unidirectional different signal channel conveys Transition Minimized Differential Signaling (TMDS) signals as digital video data.

2. The computer system of claim 1, wherein the integrated central processing unit and graphics subsystem directly couples to a second LVDS channel comprising two unidirectional, differential signal pairs transmitting data in opposite directions.

3. The computer system of claim 1, wherein the integrated central processing unit and graphics subsystem directly couples to a second LVDS channel comprising two channels of multiple, unidirectional, differential signal pairs transmitting data in opposite directions.

4. The computer system of claim 3, wherein the second LVDS channel conveys a serial bit stream of encoded address, data, and byte enable information of a Peripheral Component Interconnect (PCI) bus transaction.

5. The computer system of claim 1, wherein the TMDS signals couple to the connector.

6. The computer system of claim 2, wherein the second LVDS channel conveys Universal Serial Bus (USB) protocol data.

7. The computer system of claim 4, wherein the TMDS signals couple to the connector.

8. A computer system, comprising:

a console with a power supply; and

a computer with

an integrated central processing unit and graphics subsystem in a single chip, wherein the graphics subsystem directly couples to a unidirectional differential signal channel to output digital video data; and

a connector to couple to the console;

a first Low Voltage Differential Signal (LVDS) channel directly coupled to the connector, comprising two unidirectional, differential signal pairs transmitting data in opposite directions to convey Universal Serial Bus (USB) protocol data, and

wherein the console supplies power to the computer through the connector upon coupling.

9. The computer system of claim 8, wherein the unidirectional different signal channel conveys Transition Minimized Differential Signaling (TMDS) signals as digital video data.

10. The computer system of claim 8, wherein the console further comprises a peripheral device;

and wherein the first LVDS channel couples to the peripheral device to convey Universal Serial Bus (USB) protocol data upon connecting the console to the computer.

11. The computer system of claim 8, wherein the console further comprises a mass storage device;

and wherein the first LVDS channel couples to the mass storage device to convey Universal Serial Bus (USB) protocol data upon connecting the console to the computer.

12. The computer system of claim 9, wherein the console further comprises a display device;

and wherein the TMDS signals couple to the display device upon connecting the console to the computer.

13. A computer system, comprising:

a computer with

an integrated central processing unit and graphics subsystem in a single chip;

wherein the integrated graphics subsystem directly couples to a first Low Voltage Differential Signal (LVDS) channel comprising two unidirectional, differential signal pairs to convey data in opposite directions; and

a connector configurable for external peripheral communication;

a second LVDS channel directly coupled to the connector, comprising two unidirectional, differential signal pairs transmitting data in opposite directions to convey Universal Serial Bus (USB) protocol data for external peripheral communication.

14. The computer system of claim 13, wherein the first LVDS channel conveys Universal Serial Bus (USB) protocol data.

15. The computer system of claim 13 further comprising a different signal channel that conveys Transition Minimized Differential Signaling (TMDS) signals through the connector as digital video data.

16. A computer system, comprising:

a console with a power supply; and

a computer with

an integrated central processing unit and graphics subsystem in a single chip;

wherein the integrated central processing unit and graphics subsystem directly couples to a first Low Voltage Differential Signal (LVDS) channel comprising two unidirectional, differential signal pairs to convey data in opposite directions; and

a connector to couple to the console;

a second LVDS channel directly coupled to the connector, comprising two unidirectional, differential signal pairs transmitting data in opposite directions to convey a serial bit stream of Universal Serial Bus (USB) protocol data for external peripheral communication, and

wherein the console supplies power to the computer through the connector upon coupling.

17. The computer system of claim 16, wherein the first LVDS channel conveys a serial bit stream of Universal Serial Bus (USB) protocol data.

18. The computer system of claim 16 further comprises a different signal channel that conveys Transition Minimized Differential Signaling (TMDS) signals through the connector as digital video data.

19. A method of improving external peripheral data communication of a computer, comprising:

obtaining an integrated Central Processing Unit (CPU) with a graphics controller in a single chip;

connecting a unidirectional differential signal channel directly to the integrated CPU and graphics controller to output digital video data;

providing a connector for external peripheral data communication;

providing a first Low Voltage Differential Signal (LVDS) channel to convey Universal Serial Bus (USB) protocol data through the connector, wherein the LVDS channel comprises two unidirectional, serial bit channels that transmit data in opposite directions; and

providing a second LVDS channel through the connector to convey digital video data.

20. The method of claim 19 further comprising conveying Transition Minimized Differential Signaling (TMDS) signals as digital video data through the unidirectional differential signal channel.

21. The method of claim 20 further comprising coupling the TMDS signals through the connector.

22. The method of claim 19 further comprising conveying Transition Minimized Differential Signaling (TMDS) signals through the second LVDS channel as digital video data through the connector.