Performance estimation using configurable hardware emulation

• US 9,529,946 B1
• Filed: 11/13/2012
• Issued: 12/27/2016
• Est. Priority Date: 11/13/2012
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Schumacher, Paul R., Schelle, Graham F., Lysaght, Patrick, Frost, Alan M.
• Primary Examiner(s): Shah, Kamini S
• Assistant Examiner(s): COOK, BRIAN S
• Application Number:
  US13/676,035
• Time in Patent Office: 1,505 Days
• Field of Search: 703/14, 713/320, 713/340, 716/104, 716/103, 716/116
• US Class Current: 1/1
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 11/3062 where the monitored property is the power consumption power management in a computing system G06F1/3203
• CPC Class Codes: G06F 11/3457 Performance evaluation by simulation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An integrated circuit can include a processor operable to execute program code and an Intellectual Property (IP) modeling block. The IP modeling block can include a first port through which the IP modeling block receives first modeling data and a second port coupled to the processor through which the first IP modeling block communicates with the processor during emulation. The first IP modeling block also can include a power emulation circuit. The power emulation circuit is configured to consume a variable amount of power as specified by the first modeling data received via the first port.

Claims

1. An integrated circuit comprising:

a processor operable to execute program code;

a first intellectual property (IP) modeling block comprising;

a first port through which the first IP modeling block receives first modeling data comprising a power profile;

a second port coupled to the processor through which the first IP modeling block communicates with the processor during emulation; and

a power emulation circuit configured to consume a variable amount of power during emulation as programmed by the power profile of the first modeling data;

wherein the first IP modeling block is a circuit block implemented in programmable circuitry of the integrated circuit by loading configuration data and is programmed with the modeling data to mimic a segment of program code selected for hardware acceleration without performing a function of the segment of program code.

2. The integrated circuit of claim 1, wherein the modeling data specifies a toggle rate that is implemented by the power emulation circuit during emulation.

3. The integrated circuit of claim 1, wherein the IP modeling block further comprises:

a traffic generator configured to generate a first data traffic pattern with the processor according to the first modeling data.

4. The integrated circuit of claim 1, further comprising a second IP modeling block, wherein the second IP modeling block comprises a power emulation circuit configured to consume a variable amount of power as specified by second modeling data;

and

wherein the second IP modeling block is configured independently of the first IP modeling block.

5. The integrated circuit of claim 1, wherein the processor sends the first modeling data to the first IP modeling block.

6. The integrated circuit of claim 1, wherein the power emulation circuit comprises:

a plurality of predetermined resources of the IC; and

a driver circuit driving the plurality of predetermined resources of the IC;

wherein selected ones of the plurality of predetermined resources are enabled during emulation according to the first modeling data.

7. The integrated circuit of claim 6, wherein the driver circuit generates data that propagates through the enabled ones of the plurality of predetermined resources at a toggle rate specified by the first modeling data.

8. The integrated circuit of claim 1, further comprising:

a gating scheduler;

wherein the gating scheduler is configured to disable the first IP modeling block according to a gate schedule during emulation.

9. A method of emulating power consumption of a design for an electronic system, the method comprising:

implementing a configurable hardware platform within a programmable integrated circuit by loading configuration data, wherein the configurable hardware platform comprises an intellectual property (IP) modeling block coupled to a processor of the programmable integrated circuit;

programming the IP modeling block with a performance profile specifying a data traffic pattern implemented by a traffic generator of the IP modeling block during emulation and a power profile specifying power consumption for a power emulation circuit within the IP modeling block implemented during emulation;

wherein the IP modeling block is programmed with the performance profile to mimic a segment of program code selected for hardware acceleration without performing a function of the segment of program code; and

measuring power consumption of the programmable integrated circuit while the configurable hardware platform is implemented within the programmable integrated circuit.

10. The method of claim 9, wherein the configurable hardware platform comprises a plurality of IP modeling blocks;

wherein each IP modeling block is assigned to one of a plurality of different power islands; and

wherein each IP modeling block is enabled and disabled according to a gating schedule regulating activation of the power islands during emulation.

11. The method of claim 9, wherein measuring power consumption of the programmable integrated circuit comprises:

measuring dynamic power consumption of the programmable integrated circuit during emulation with the configurable hardware platform implemented within the programmable integrated circuit during emulation.

12. The method of claim 9, further comprising:

measuring static power consumption of the programmable integrated circuit with the configurable hardware platform implemented within the programmable integrated circuit without conducting emulation using the configurable hardware platform.

13. The method of claim 9, further comprising:

measuring power consumption of the programmable integrated circuit while the power emulation circuit of the IP modeling block is not active and the traffic generator generates a data traffic pattern;

or

measuring power consumption of the programmable integrated circuit while the power emulation circuit of the IP modeling block is active and the traffic generator does not generate a data traffic pattern.

14. The method of claim 9, further comprising:

measuring a temperature of the programmable integrated circuit as the IP modeling block is enabled and disabled during emulation.