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Methods, architecture, and apparatus for implementing machine intelligence and hierarchical memory systems

  • US 9,530,091 B2
  • Filed: 04/03/2012
  • Issued: 12/27/2016
  • Est. Priority Date: 12/10/2004
  • Status: Active Grant
First Claim
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1. A computer system comprising:

  • a processor; and

    a memory coupled to the processor, the memory comprising;

    a first lower level processing unit configured to receive a first portion of an input data at a first time and generate a first output representing information about temporal sequences of spatial patterns in the first portion of the input data corresponding to first learned temporal sequences of spatial patterns;

    a second lower level processing unit configured to receive a second portion of the input data at the first time and generate a second output representing information about temporal sequences of spatial patterns in the second portion of the input data corresponding to second learned temporal sequences of spatial patterns; and

    an upper level processing unit associated with the first and second lower level processing units, the upper level processing unit configured to generate a third output based on the first and the second outputs, the third output sent to at least one of the first and second lower level processing unit as a first prediction of spatial patterns in the first portion of the input data to be received by the first lower level processing unit or the second portion of the input data to be received by the second lower level processing node at a second time subsequent to the first time.

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