Packing multiple shader programs onto a graphics processor

• US 9,530,245 B2
• Filed: 12/07/2012
• Issued: 12/27/2016
• Est. Priority Date: 12/29/2011
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Frascati, Christopher Paul, Seetharamaiah, Avinash, Blankenship, Joseph
• Primary Examiner(s): Drennan, Barry
• Assistant Examiner(s): CRADDOCK, ROBERT J
• Application Number:
  US13/708,118
• Publication Number:
  US 20130169642A1
• Time in Patent Office: 1,481 Days
• Field of Search: 345/426, 345/522, 711/130, 711/100, 711/135, 711/129, 711/133, 711/143, 711/159, 711/132, 718/1, 718/100
• US Class Current: 1/1
• CPC Class Codes: G06F 9/445 Program loading or initiating bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57
• CPC Class Codes: G06F 9/44594 Unloading
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 11/00 2D [Two Dimensional] image generation
• CPC Class Codes: G06T 15/04 Texture mapping
• CPC Class Codes: G06T 15/80 Shading
• CPC Class Codes: G06T 15/83 Phong shading
• CPC Class Codes: G06T 17/10 Constructive solid geometry [CSG] using solid primitives, e.g. cylinders, cubes
• CPC Class Codes: G06T 17/20 Finite element generation, e.g. wire-frame surface description, tesselation
• CPC Class Codes: G06T 7/40 Analysis of texture depth or shape recovery from texture G06T7/529

Abstract

This disclosure describes techniques for packing multiple shader programs of a common shader program type onto a graphics processing unit (GPU). The techniques may include, for example, causing a plurality of shader programs of a common shader program type to be loaded into an on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time. In addition, various techniques for evicting shader programs from an on-chip shader program instruction memory are described.

Claims

1. A method comprising:

causing a plurality of shader programs of a common shader program type to be loaded into an on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time, wherein causing the plurality of shader programs of the common shader program type to be loaded comprises;

loading a first shader program of the common shader program type into the on-chip shader program instruction memory;

determining one or more ranges of available memory space in the on-chip shader program instruction memory after the first shader program has been loaded into the on-chip shader program instruction memory;

loading a second shader program of the common shader program type into one of the one or more ranges of available memory space;

determining whether the on-chip shader program instruction memory has a sufficient amount of available memory space to store a shader program to be loaded into the on-chip shader program instruction memory; and

in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program;

determining a least frequently used shader program from a set of one or more shader programs stored within the on-chip shader program instruction memory; and

evicting the least frequently used shader program from the on-chip shader program instruction memory,

wherein the on-chip shader program instruction memory comprises an instruction cache from which a shader unit fetches instructions during execution of at least one of the plurality of shader programs.

2. The method of claim 1, wherein the common shader program type comprises a shader program type that is indicative of at least one of a type of data upon which the shader program is configured to operate and a type of operation performed by the shader program.

3. The method of claim 1, wherein the common shader program type comprises one of a vertex shader program type, a pixel shader program type, a geometry shader program type, a hull shader program type, a domain shader program type, and a compute shader program type.

4. The method of claim 1, wherein loading the second shader program of the common shader program type into the on-chip shader program instruction memory is performed without overwriting the first shader program.

5. The method of claim 1, wherein evicting the shader program from the on-chip shader program instruction memory comprises:

overwriting at least a portion of the evicted shader program with at least a portion of the shader program to be loaded into the on-chip shader program instruction memory.

6. A device comprising:

an on-chip shader program instruction memory comprising an instruction cache from which a shader unit fetches instructions during execution of at least one of a plurality of shader programs;

a processor configured to;

cause the plurality of shader programs of a common shader program type to be loaded into the on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time;

load a first shader program of the common shader program type into the on-chip shader program instruction memory;

determine one or more ranges of available memory space in the on-chip shader program instruction memory after the first shader program has been loaded into the on-chip shader program instruction memory;

load a second shader program of the common shader program type into one of the one or more ranges of available memory space;

determine whether the on-chip shader program instruction memory has a sufficient amount of available memory space to store a shader program to be loaded into the on-chip shader program instruction memory;

determine a least frequently used shader program from a set of one or more shader programs stored within the on-chip shader program instruction memory; and

evict the least frequently used shader program from the on-chip shader program instruction memory in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program.

7. The device of claim 6, wherein the common shader program type comprises a shader program type that is indicative of at least one of a type of data upon which the shader program is configured to operate and a type of operation performed by the shader program.

8. The device of claim 6, wherein the common shader program type comprises one of a vertex shader program type, a pixel shader program type, a geometry shader program type, a hull shader program type, a domain shader program type, and a compute shader program type.

9. The device of claim 6, wherein the processor is further configured to load a the second shader program of the common shader program type into the on-chip shader program instruction memory without overwriting the first shader program.

10. The device of claim 6, wherein the processor is further configured to overwrite at least a portion of the evicted shader program with at least a portion of the shader program to be loaded into the on-chip shader program instruction memory.

11. The device of claim 6, wherein the device comprises a wireless communication device.

12. The device of claim 6, wherein the device comprises a mobile phone handset.

13. An apparatus comprising:

means for loading a shader program into an on-chip shader program instruction memory of a graphics processor;

means for causing a plurality of shader programs of a common shader program type to be loaded into the on-chip shader program instruction memory of the graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time;

means for loading a first shader program of the common shader program type into the on-chip shader program instruction memory;

means for determining one or more ranges of available memory space in the on-chip shader program instruction memory after the first shader program has been loaded into the on-chip shader program instruction memory;

means for loading a second shader program of the common shader program type into one of the one or more ranges of available memory space;

means for determining whether the on-chip shader program instruction memory has a sufficient amount of available memory space to store a shader program to be loaded into the on-chip shader program instruction memory;

means for determining a least frequently used shader program from a set of one or more shader programs stored within the on-chip shader program instruction memory in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program; and

means for evicting the least frequently used shader program from the on-chip shader program instruction memory in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program,

wherein the on-chip shader program instruction memory comprises an instruction cache from which a shader unit fetches instructions during execution of at least one of the plurality of shader programs.

14. The apparatus of claim 13, wherein the common shader program type comprises a shader program type that is indicative of at least one of a type of data upon which the shader program is configured to operate and a type of operation performed by the shader program.

15. The apparatus of claim 13, wherein the common shader program type comprises one of a vertex shader program type, a pixel shader program type, a geometry shader program type, a hull shader program type, a domain shader program type, and a compute shader program type.

16. The apparatus of claim 13, wherein the means for loading a second shader program of the common shader program type into the on-chip shader program instruction memory loads the second shader program without overwriting the first shader program.

17. The apparatus of claim 13, wherein the means for evicting the shader program from the on-chip shader program instruction memory comprises:

means for overwriting at least a portion of the evicted shader program with at least a portion of the shader program to be loaded into the on-chip shader program instruction memory.

18. A non-transitory computer-readable storage medium storing instructions that, when executed, cause one or more processors to:

cause a plurality of shader programs of a common shader program type to be loaded into an on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time;

load a first shader program of the common shader program type into the on-chip shader program instruction memory;

determine one or more ranges of available memory space in the on-chip shader program instruction memory after the first shader program has been loaded into the on-chip shader program instruction memory;

load a second shader program of the common shader program type into one of the one or more ranges of available memory space;

determine whether the on-chip shader program instruction memory has a sufficient amount of available memory space to store a shader program to be loaded into the on-chip shader program instruction memory; and

in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program;

determine a least frequently used shader program from a set of one or more shader programs stored within the on-chip shader program instruction memory; and

evict the least frequently used shader program from the on-chip shader program instruction memory,

wherein the on-chip shader program instruction memory comprises an instruction cache from which a shader unit fetches instructions during execution of at least one of the plurality of shader programs.

19. The non-transitory computer-readable storage medium of claim 18, wherein the common shader program type comprises a shader program type that is indicative of at least one of a type of data upon which the shader program is configured to operate and a type of operation performed by the shader program.

20. The non-transitory computer-readable storage medium of claim 18, wherein the common shader program type comprises one of a vertex shader program type, a pixel shader program type, a geometry shader program type, a hull shader program type, a domain shader program type, and a compute shader program type.

21. The non-transitory computer-readable storage medium of claim 18, wherein the instructions further cause the one or more processors to:

load a second shader program of the common shader program type into the on-chip shader program instruction memory without overwriting the first shader program.

22. The non-transitory computer-readable storage medium of claim 18, wherein the instructions that cause the one or more processors to evict the shader program from the on-chip shader program instruction memory comprise instructions that cause the one or more processors to:

overwrite at least a portion of the evicted shader program with at least a portion of the shader program to be loaded into the on-chip shader program instruction memory.

23. A method comprising:

causing a plurality of shader programs of a common shader program type to be loaded into an on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time, wherein causing the plurality of shader programs of the common shader program type to be loaded comprises;

loading a first shader program of the common shader program type into the on-chip shader program instruction memory;

determining one or more ranges of available memory space in the on-chip shader program instruction memory after the first shader program has been loaded into the on-chip shader program instruction memory;

loading a second shader program of the common shader program type into one of the one or more ranges of available memory space;

determining whether the on-chip shader program instruction memory has a sufficient amount of available memory space to store a shader program to be loaded into the on-chip shader program instruction memory; and

in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program,

determining a least recently used shader program from a set of one or more shader programs stored within the on-chip shader program instruction memory; and

evicting the least recently used shader program from the on-chip shader program instruction memory,

wherein the on-chip shader program instruction memory comprises an instruction cache from which a shader unit fetches instructions during execution of at least one of the plurality of shader programs.

24. The method of claim 23, wherein loading the second shader program of the common shader program type into the on-chip shader program instruction memory is performed without overwriting the first shader program.

25. The method of claim 23, wherein evicting the shader program from the on-chip shader program instruction memory comprises:

overwriting at least a portion of the evicted shader program with at least a portion of the shader program to be loaded into the on-chip shader program instruction memory.

26. A method comprising:

causing a plurality of shader programs of a common shader program type to be loaded into an on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time, wherein causing the plurality of shader programs of the common shader program type to be loaded comprises;

loading a first shader program of the common shader program type into the on-chip shader program instruction memory;

determining one or more ranges of available memory space in the on-chip shader program instruction memory after the first shader program has been loaded into the on-chip shader program instruction memory;

loading a second shader program of the common shader program type into one of the one or more ranges of available memory space;

determining whether the on-chip shader program instruction memory has a sufficient amount of available memory space to store a shader program to be loaded into the on-chip shader program instruction memory; and

in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program;

determining a set of N least frequently used shader programs from a set of one or more shader programs stored within the on-chip shader program instruction memory, where N is an integer greater than or equal to one;

determining a least recently used shader program from the set of N least frequently used shader programs; and

evicting the least recently used shader program from the on-chip shader program instruction memory,

wherein the on-chip shader program instruction memory comprises an instruction cache from which a shader unit fetches instructions during execution of at least one of the plurality of shader programs.

27. The method of claim 26, wherein loading the second shader program of the common shader program type into the on-chip shader program instruction memory is performed without overwriting the first shader program.

28. The method of claim 26, wherein evicting the shader program from the on-chip shader program instruction memory comprises:

overwriting at least a portion of the evicted shader program with at least a portion of the shader program to be loaded into the on-chip shader program instruction memory.

29. A device comprising:

an on-chip shader program instruction memory comprising an instruction cache from which a shader unit fetches instructions during execution of at least one of a plurality of shader programs;

a processor configured to;

cause the plurality of shader programs of a common shader program type to be loaded into the on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time;

load a first shader program of the common shader program type into the on-chip shader program instruction memory;

determine one or more ranges of available memory space in the on-chip shader program instruction memory after the first shader program has been loaded into the on-chip shader program instruction memory;

load a second shader program of the common shader program type into one of the one or more ranges of available memory space;

determine whether the on-chip shader program instruction memory has a sufficient amount of available memory space to store a shader program to be loaded into the on-chip shader program instruction memory;

determine a least recently used shader program from a set of one or more shader programs stored within the on-chip shader program instruction memory; and

evict the least recently used shader program from the on-chip shader program instruction memory in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program.

30. The device of claim 29, wherein the processor is further configured to load a the second shader program of the common shader program type into the on-chip shader program instruction memory without overwriting the first shader program.

31. The device of claim 29, wherein the processor is further configured to overwrite at least a portion of the evicted shader program with at least a portion of the shader program to be loaded into the on-chip shader program instruction memory.

32. A device comprising:

an on-chip shader program instruction memory comprising an instruction cache from which a shader unit fetches instructions during execution of at least one of a plurality of shader programs;

a processor configured to;

cause the plurality of shader programs of a common shader program type to be loaded into the on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time;

load a first shader program of the common shader program type into the on-chip shader program instruction memory;

determine one or more ranges of available memory space in the on-chip shader program instruction memory after the first shader program has been loaded into the on-chip shader program instruction memory;

load a second shader program of the common shader program type into one of the one or more ranges of available memory space;

determine whether the on-chip shader program instruction memory has a sufficient amount of available memory space to store a shader program to be loaded into the on-chip shader program instruction memory;

determine a set of N least frequently used shader programs from a set of one or more shader programs stored within the on-chip shader program instruction memory;

determine a least recently used shader program from the set of N least frequently used shader programs; and

evict the least recently used shader program from the on-chip shader program instruction memory, where N is an integer greater than or equal to one in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program.

33. The device of claim 32, wherein the processor is further configured to load a the second shader program of the common shader program type into the on-chip shader program instruction memory without overwriting the first shader program.

34. The device of claim 32, wherein the processor is further configured to overwrite at least a portion of the evicted shader program with at least a portion of the shader program to be loaded into the on-chip shader program instruction memory.

35. An apparatus comprising:

means for loading a shader program into an on-chip shader program instruction memory of a graphics processor;

means for causing a plurality of shader programs of a common shader program type to be loaded into the on-chip shader program instruction memory of the graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time;

means for loading a first shader program of the common shader program type into the on-chip shader program instruction memory;

means for determining one or more ranges of available memory space in the on-chip shader program instruction memory after the first shader program has been loaded into the on-chip shader program instruction memory;

means for loading a second shader program of the common shader program type into one of the one or more ranges of available memory space;

means for determining whether the on-chip shader program instruction memory has a sufficient amount of available memory space to store a shader program to be loaded into the on-chip shader program instruction memory;

means for determining a least recently used shader program from a set of one or more shader programs stored within the on-chip shader program instruction memory in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program; and

means for evicting the least recently used shader program from the on-chip shader program instruction memory in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program,

wherein the on-chip shader program instruction memory comprises an instruction cache from which a shader unit fetches instructions during execution of at least one of the plurality of shader programs.

36. The apparatus of claim 35, wherein the means for loading a second shader program of the common shader program type into the on-chip shader program instruction memory loads the second shader program without overwriting the first shader program.

37. An apparatus comprising:

means for loading a shader program into an on-chip shader program instruction memory of a graphics processor;

means for causing a plurality of shader programs of a common shader program type to be loaded into the on-chip shader program instruction memory of the graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time;

means for loading a first shader program of the common shader program type into the on-chip shader program instruction memory;

means for determining one or more ranges of available memory space in the on-chip shader program instruction memory after the first shader program has been loaded into the on-chip shader program instruction memory;

means for loading a second shader program of the common shader program type into one of the one or more ranges of available memory space;

means for determining whether the on-chip shader program instruction memory has a sufficient amount of available memory space to store a shader program to be loaded into the on-chip shader program instruction memory;

means for determining a set of N least frequently used shader programs from a set of one or more shader programs stored within the on-chip shader program instruction memory, where N is an integer greater than or equal to one in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program;

means for determining a least recently used shader program from the set of N least frequently used shader programs in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program; and

means for evicting the least recently used shader program from the on-chip shader program instruction memory in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program,

wherein the on-chip shader program instruction memory comprises an instruction cache from which a shader unit fetches instructions during execution of at least one of the plurality of shader programs.

38. The apparatus of claim 37, wherein the means for loading a second shader program of the common shader program type into the on-chip shader program instruction memory loads the second shader program without overwriting the first shader program.

39. A non-transitory computer-readable storage medium storing instructions that, when executed, cause one or more processors to:

cause a plurality of shader programs of a common shader program type to be loaded into an on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time;

load a first shader program of the common shader program type into the on-chip shader program instruction memory;

determine one or more ranges of available memory space in the on-chip shader program instruction memory after the first shader program has been loaded into the on-chip shader program instruction memory;

load a second shader program of the common shader program type into one of the one or more ranges of available memory space;

determine whether the on-chip shader program instruction memory has a sufficient amount of available memory space to store a shader program to be loaded into the on-chip shader program instruction memory; and

in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program;

determine a least recently used shader program from a set of one or more shader programs stored within the on-chip shader program instruction memory; and

evict the least recently used shader program from the on-chip shader program instruction memory,

wherein the on-chip shader program instruction memory comprises an instruction cache from which a shader unit fetches instructions during execution of at least one of the plurality of shader programs.

40. The non-transitory computer-readable storage medium of claim 39, wherein the instructions further cause the one or more processors to:

load a second shader program of the common shader program type into the on-chip shader program instruction memory without overwriting the first shader program.

41. A non-transitory computer-readable storage medium storing instructions that, when executed, cause one or more processors to:

cause a plurality of shader programs of a common shader program type to be loaded into an on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time;

load a first shader program of the common shader program type into the on-chip shader program instruction memory;

determine one or more ranges of available memory space in the on-chip shader program instruction memory after the first shader program has been loaded into the on-chip shader program instruction memory;

load a second shader program of the common shader program type into one of the one or more ranges of available memory space;

determine whether the on-chip shader program instruction memory has a sufficient amount of available memory space to store a shader program to be loaded into the on-chip shader program instruction memory; and

in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program;

determine a set of N least frequently used shader programs from a set of one or more shader programs stored within the on-chip shader program instruction memory, where N is an integer greater than or equal to one;

determine a least recently used shader program from the set of N least frequently used shader programs; and

evict the least recently used shader program from the on-chip shader program instruction memory,

wherein the on-chip shader program instruction memory comprises an instruction cache from which a shader unit fetches instructions during execution of at least one of the plurality of shader programs.

42. The non-transitory computer-readable storage medium of claim 41, wherein the instructions further cause the one or more processors to:

load a second shader program of the common shader program type into the on-chip shader program instruction memory without overwriting the first shader program.