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System and method for retaining dram data when reprogramming reconfigurable devices with DRAM memory controllers incorporating a data maintenance block colocated with a memory module or subsystem

  • US 9,530,483 B2
  • Filed: 08/24/2015
  • Issued: 12/27/2016
  • Est. Priority Date: 05/27/2014
  • Status: Active Grant
First Claim
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1. A computer system comprising:

  • a DRAM memory;

    a reconfigurable logic device having a memory controller coupled to selected inputs and outputs of said DRAM memory; and

    a data maintenance block collocated with said DRAM memory and coupled to said reconfigurable logic device and self-refresh command inputs of said DRAM memory, said data maintenance block operative to provide stable input levels on said self-refresh command inputs while said reconfigurable logic device is reconfigured.

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