System and method for retaining dram data when reprogramming reconfigurable devices with DRAM memory controllers incorporating a data maintenance block colocated with a memory module or subsystem

• US 9,530,483 B2
• Filed: 08/24/2015
• Issued: 12/27/2016
• Est. Priority Date: 05/27/2014
• Status: Active Grant

• Current Assignee: FG SRC LLC (Freeman Capital Partners LP)
• Original Assignee: SRC Labs, LLC (Freeman Capital Partners LP)
• Inventors: Tewalt, Timothy J.
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US14/834,273
• Publication Number:
  US 20150364182A1
• Time in Patent Office: 491 Days
• Field of Search: 365/222
• US Class Current: 1/1
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 2212/68 Details of translation look-aside buffer [TLB]
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0632 by initialisation or re-initialisation of storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting

Abstract

A system and method for retaining dynamic random access memory (DRAM) data when reprogramming reconfigurable devices with DRAM memory controllers such as field programmable gate arrays (FPGAs). The DRAM memory controller is utilized in concert with a data maintenance block collocated with the DRAM memory and coupled to an I2C interface of the reconfigurable device, wherein the FPGA drives the majority of the DRAM input/output (I/O) and the data maintenance block drives the self-refresh command inputs. Even though the FPGA reconfigures and the majority of the DRAM inputs are tri-stated, the data maintenance block provides stable input levels on the self-refresh command inputs.

Claims

1. A computer system comprising:

a DRAM memory;

a reconfigurable logic device having a memory controller coupled to selected inputs and outputs of said DRAM memory; and

a data maintenance block collocated with said DRAM memory and coupled to said reconfigurable logic device and self-refresh command inputs of said DRAM memory, said data maintenance block operative to provide stable input levels on said self-refresh command inputs while said reconfigurable logic device is reconfigured.

2. The computer system of claim 1 wherein said data maintenance block is located on a module with said DRAM memory.

3. The computer system of claim 2 wherein said module comprises a DIMM module.

4. The computer system of claim 1 wherein said data maintenance block further comprises a serial presence detect storage device.

5. The computer system of claim 1 wherein data maintenance block is further coupled to a communication port of said reconfigurable logic device.

6. The computer system of claim 5 wherein said communication port comprises an I2C interface.

7. The computer system of claim 5 wherein said communication port provides power up/down requests and data read/write accesses to said data maintenance block.

8. The computer system of claim 1 wherein said DRAM memory comprises DDR3 compliant memory devices.

9. The computer system of claim 1 wherein said reconfigurable logic device comprises an FPGA.

10. The computer system of claim 1 wherein said data maintenance block comprises a memory block coupled to a reconfigure controller of said reconfigurable logic device.

11. The computer system of claim 10 wherein said memory block is operative to retain data received from said reconfigure controller of said reconfigurable logic device.

12. The computer system of claim 1 wherein said data maintenance block comprises a CPLD.

13. The computer system of claim 1 wherein said data maintenance block is operable to hold said DRAM memory in self-refresh mode while said reconfigurable logic device is reconfigured.

14. The computer system of claim 1 wherein said data maintenance block is operative to maintain data in said DRAM memory while said reconfigurable logic device and memory controller is removed from said computer system and replaced with a second reconfigurable logic device and memory controller.

15. A method for preserving contents of a DRAM memory associated with a reconfigurable device having a memory controller comprising:

providing a data maintenance block collocated with said DRAM memory, said data maintenance block being coupled to said reconfigurable device;

coupling said data maintenance block to self-refresh command inputs of said DRAM memory;

storing data received from said reconfigurable device at said data maintenance block; and

maintaining stable input levels on said self-refresh command inputs while said reconfigurable logic device is reconfigured.

16. The method of claim 15 further comprising:

locating said data maintenance block on a module comprising said DRAM memory.

17. The method of claim 16 wherein said module comprises a DIMM module.

18. The method of claim 15 further comprising:

also providing a serial presence detect storage device associated with said data maintenance block.

19. The method of claim 15 further comprising:

also coupling said data maintenance block to a communications port of said reconfigurable device.

20. The method of claim 19 wherein said communications port comprises an I2C interface.

21. The method of claim 19 wherein said communications port is operative to provide power up/down requests and data read/write accesses to said data maintenance block.

22. The method of claim 15 wherein said reconfigurable device comprises an FPGA.

23. The method of claim 15 wherein said data maintenance block comprises a CPLD.

24. The method of claim 15 further comprising:

holding said DRAM memory is self-refresh mode with said data maintenance block while said reconfigurable device is reconfigured.

25. The method of claim 15 further comprising:

maintaining data in said DRAM memory while said reconfigurable device and said memory controller is removed from a computer system comprising the same and replaced with a second reconfigurable device and memory controller.