NAND boosting using dynamic ramping of word line voltages

• US 9,530,506 B2
• Filed: 11/21/2014
• Issued: 12/27/2016
• Est. Priority Date: 11/21/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Rabkin, Peter, Dong, Yingda, Higashitani, Masaaki
• Primary Examiner(s): Graham, Kretelia
• Application Number:
  US14/550,897
• Publication Number:
  US 20160148691A1
• Time in Patent Office: 767 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be improved. In one example, the slope and timing of a Vpass waveform applied to a group of unselected word lines (e.g., the neighboring word lines of the selected word line) during the programming operation may be set based on the location of the selected word line within the memory array and the locations of the group of unselected word lines within the memory array.

Claims

1. A method for operating a non-volatile storage system, comprising:

acquiring data to be programmed into a set of memory cells within a memory array;

determining a programming waveform to be applied to a selected word line connected to the set of memory cells, the programming waveform includes a voltage ramp to a programming voltage;

determining a first voltage waveform to be applied to a first grouping of unselected word lines within the memory array, the first voltage waveform includes a first initial ramp to a first initial voltage and a first final ramp to a pass voltage, the pass voltage is greater than the first initial voltage, the pass voltage is less than the programming voltage;

determining a second grouping of unselected word lines within the memory array different from the first grouping of unselected word lines;

determining a second voltage waveform to be applied to the second grouping of unselected word lines, the second voltage waveform includes a second initial ramp to a second initial voltage and a second final ramp from the second initial voltage to the pass voltage; and

performing a programming operation to program the data into the set of memory cells, the programming operation includes applying the programming voltage waveform to the selected word line and applying the first voltage waveform to the first grouping of unselected word lines such that the first final ramp to the pass voltage occurs after the selected word line has been set to the programming voltage, the pass voltage comprises a maximum voltage applied to the first grouping of unselected word lines during the programming operation, the programming operation includes applying the second voltage waveform to the second grouping of unselected word lines such that the second final ramp to the pass voltage occurs after the selected word line has been set to the programming voltage.

2. The method of claim 1, wherein:

the programming operation includes applying the voltage ramp to the selected word line at substantially the same time as applying the first initial ramp to the first grouping of unselected word lines.

3. The method of claim 1, wherein:

the first initial ramp to the first initial voltage is steeper than the first final ramp to the pass voltage.

4. The method of claim 1, wherein:

the voltage ramp to the programming voltage is steeper than the first final ramp to the pass voltage.

5. The method of claim 1, wherein:

the first final ramp is from the first initial voltage to the pass voltage, the first final ramp occurs subsequent to the voltage ramp to the programming voltage.

6. The method of claim 1, further comprising:

determining a location of the selected word line within the memory array; and

determining the first grouping of unselected word lines based on the location of the selected word line.

7. The method of claim 1, wherein:

the first final ramp to the pass voltage is steeper than the second final ramp to the pass voltage.

8. The method of claim 1, wherein:

the first initial voltage is different from the second initial voltage.

9. The method of claim 1, wherein:

the applying the first voltage waveform to the first grouping of unselected word lines includes applying the first voltage waveform to a first word line within the memory array adjacent to the selected word line; and

the applying the second voltage waveform to the second grouping of unselected word lines includes applying the second voltage waveform to a second word line within the memory array adjacent to the first word line.

10. The method of claim 1, wherein:

the applying the first voltage waveform to the first grouping of unselected word lines includes applying the first voltage waveform such that a continuous voltage ramping of the first grouping of unselected word lines occurs throughout the programming operation.

11. The method of claim 1, wherein:

the memory array comprises a NAND memory array.

12. The method of claim 1, wherein:

the memory array comprises a non-volatile memory that is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.

13. The method of claim 1, wherein:

the memory array comprises a three-dimensional memory array.

14. A non-volatile storage system, comprising:

a memory array, the memory array includes a set of memory cells; and

one or more managing circuits in communication with the memory array, the one or more managing circuits configured to acquire data to be programmed into the set of memory cells and configured to determine a programming waveform to be applied to a selected word line connected to the set of memory cells, the programming waveform includes a voltage ramp to a programming voltage, the one or more managing circuits configured to determine a first voltage waveform to be applied to a first grouping of unselected word lines within the memory array, the first voltage waveform includes a first initial ramp to a first initial voltage and a first final ramp to a pass voltage, the pass voltage is greater than the first initial voltage, the pass voltage is less than the programming voltage, the one or more managing circuits configured to initiate a programming operation to program the data into the set of memory cells, the one or more managing circuits configured to cause the programming voltage waveform to be applied to the selected word line during the programming operation and configured to cause the first voltage waveform to be applied to the first grouping of unselected word lines during the programming operation such that the first final ramp to the pass voltage occurs after the selected word line has been set to the programming voltage, the pass voltage comprises a maximum voltage applied to the first grouping of unselected word lines during the programming operation, the one or more managing circuits configured to determine a second grouping of unselected word lines within the memory array different from the first grouping of unselected word lines and determine a second voltage waveform to be applied to the second grouping of unselected word lines, the second voltage waveform includes a second initial ramp to a second initial voltage and a second final ramp from the second initial voltage to the pass voltage, the one or more managing circuits configured to apply the second voltage waveform to the second grouping of unselected word lines such that the second final ramp to the pass voltage occurs after the selected word line has been set to the programming voltage.

15. The non-volatile storage system of claim 14, wherein:

the one or more managing circuits configured to cause the voltage ramp to be applied to the selected word line at substantially the same time as the first initial ramp is applied to the first grouping of unselected word lines.

16. The non-volatile storage system of claim 14, wherein:

the first initial ramp to the first initial voltage is steeper than the first final ramp to the pass voltage.

17. The non-volatile storage system of claim 14, wherein:

the voltage ramp to the programming voltage is steeper than the first final ramp to the pass voltage.

18. The non-volatile storage system of claim 14, wherein:

the memory array comprises a three-dimensional memory array.

19. A method for operating a non-volatile storage system, comprising:

acquiring data to be programmed into a set of floating gate transistors within a memory array;

determining a programming waveform to be applied to a selected word line connected to the set of floating gate transistors, the programming waveform includes a voltage ramp to a programming voltage;

determining a first voltage waveform to be applied to a first grouping of unselected word lines within the memory array, the first voltage waveform includes a first ramp to a pass voltage, the pass voltage is less than the programming voltage;

determining a second grouping of unselected word lines within the memory array different from the first grouping of unselected word lines;

determining a second voltage waveform to be applied to the second grouping of unselected word lines, the second voltage waveform includes a second initial ramp to a second initial voltage and a second final ramp from the second initial voltage to the pass voltage; and

performing a programming operation to program the data into the set of floating gate transistors, the programming operation includes applying the programming voltage waveform to the selected word line and applying the first voltage waveform to the first grouping of unselected word lines such that a continuous voltage ramping of the first grouping of unselected word lines occurs throughout the programming operation, the pass voltage comprises a maximum voltage applied to the first grouping of unselected word lines during the programming operation, the programming operation includes applying the second voltage waveform to the second grouping of unselected word lines such that the second final ramp to the pass voltage occurs after the selected word line has been set to the programming voltage.