Temperature dependent sensing scheme to counteract cross-temperature threshold voltage distribution widening

• US 9,530,512 B2
• Filed: 12/17/2014
• Issued: 12/27/2016
• Est. Priority Date: 09/19/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Ray, Biswajit, Dogan, Abuzer, Chen, Changyuan
• Primary Examiner(s): Norman, James G
• Application Number:
  US14/574,110
• Publication Number:
  US 20160086674A1
• Time in Patent Office: 741 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

Methods for reducing cross-temperature threshold voltage distribution widening by applying a temperature dependent sensing scheme during read operations are described. In some embodiments, during a read operation, the sensing conditions applied to memory cells within a memory array (e.g., the sensing time and the read voltage applied to the memory cells during the sensing time) may be set and/or adjusted based on a temperature of the memory cells during the read operation, a previous temperature of the memory cells when the memory cells were programmed, and the programmed states of neighboring memory cells. In some cases, the sensing time for sensing a memory cell of a NAND string and the source voltage applied to a source line connected to the NAND string may be set based on the temperature of the memory cells during sensing and the previous temperature of the memory cells when the memory cells were programmed.

Claims

1. A non-volatile storage system, comprising:

a memory array, the memory array includes a first memory cell that is part of a first NAND string; and

one or more control circuits configured to determine a programmed temperature at which data was last programmed into the first memory cell and determine a source line voltage based on the programmed temperature and a read temperature at which the first memory cell will be read, the one or more control circuits configured to set a source line of the first NAND string to the source line voltage while the data is read from the first memory cell.

2. The non-volatile storage system of claim 1, wherein:

the one or more control circuits configured to determine a bit line voltage to be applied to a bit line connected to the first NAND string based on the programmed temperature and the read temperature, the bit line voltage is applied to the bit line while the data is read from the first memory cell.

3. The non-volatile storage system of claim 1, wherein:

the one or more control circuits configured to determine a neighboring data state of a second memory cell that is adjacent to the first memory cell; and

the one or more control circuits configured to determine a sensing time from the first memory cell based on the programmed temperature, the read temperature, and the neighboring data state.

4. The non-volatile storage system of claim 2, wherein:

the one or more control circuits configured to determine an integration capacitance value to be used during a sensing time based on the programmed temperature and the read temperature, a current through the first NAND string discharges an integration capacitor of the integration capacitance value during the sensing time while the data is read from the first memory cell.

5. The non-volatile storage system of claim 4, wherein:

the integration capacitor is sampled after the sensing time has passed.

6. The non-volatile storage system of claim 1, wherein:

the data comprises a page of data; and

the one or more control circuits configured to reduce the source line voltage if the read temperature is less than the programmed temperature.

7. The non-volatile storage system of claim 6, wherein:

the one or more control circuits configured to acquire temperature information from a sideband area associated with the page and configured to determine the programmed temperature based on the temperature information.

8. The non-volatile storage system of claim 1, wherein:

the first NAND string comprises a vertical NAND string.

9. The non-volatile storage system of claim 1, wherein:

the plurality of memory cells are part of a memory array, the memory array is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.

10. The non-volatile storage system of claim 1, wherein:

the plurality of memory cells are part of a memory array, the memory array comprises a three-dimensional memory array.

11. A method for operating a non-volatile storage system, comprising:

determining a programmed temperature at which data was last programmed into a first memory cell that is a part of a first NAND string;

determining a read temperature at which the first memory cell will be read;

determining a source line voltage based on the programmed temperature and the read temperature; and

performing a read operation to read the data from the first memory cell, the read operation includes applying the source line voltage to a source line of the first NAND string.

12. The method of claim 11, further comprising:

determining a sensing time based on the programmed temperature and the read temperature; and

determining a bit line voltage to be applied to a bit line connected to the first NAND string based on the programmed temperature and the read temperature, the read operation includes applying the bit line voltage to the bit line for the sensing time.

13. The method of claim 12, further comprising:

determining a neighboring data state of a second memory cell that is adjacent to the first memory cell; and

determining the sensing time based on the programmed temperature, the read temperature, and the neighboring data state.

14. The method of claim 11, further comprising:

determining an integration capacitance value to be used during a sensing time based on the programmed temperature and the read temperature, the read operation includes discharging an integration capacitor of the integration capacitance value during the sensing time using a current through the first NAND string.

15. The method of claim 14, wherein:

the read operation includes sampling the integration capacitor after the sensing time has passed.

16. The method of claim 11, wherein:

the data comprises a page of data; and

the determining the source line voltage includes reducing the source line voltage if the read temperature is less than the programmed temperature.

17. The method of claim 16, wherein:

the determining a programmed temperature includes acquiring temperature information from a sideband area associated with the page and decoding the temperature information.

18. The method of claim 11, wherein:

the first NAND string comprises a vertical NAND string.

19. The method of claim 11, wherein:

the plurality of memory cells are part of a three-dimensional memory.

20. An apparatus, comprising:

a plurality of memory cells, the plurality of memory cells includes a first memory cell that is part of a first NAND string; and

one or more control circuits in communication with the plurality of memory cells, the one or more control circuits configured to determine a programmed temperature of the plurality of memory cells at which data was last programmed into the plurality of memory cells and configured to determine a read temperature at which the plurality of memory cells will be read, the one or more control circuits configured to determine a source line voltage based on the programmed temperature and the read temperature, the one or more control circuits configured to determine a threshold voltage of the first memory cell during a sensing operation, the source line voltage is applied to a source line of the first NAND string during the sensing operation.