Sorting non-volatile memories

• US 9,530,522 B1
• Filed: 03/10/2016
• Issued: 12/27/2016
• Est. Priority Date: 01/28/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Christensen, Jeffrey W., Christensen, Phillip E., Moore, Daniel E., Sater, Antoine G., Yoon, Jung H.
• Primary Examiner(s): NIKMANESH, SEAHVOSH J
• Application Number:
  US15/066,178
• Time in Patent Office: 292 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

A computer-implemented method for sorting non-volatile random access memories (NVRAMS) includes testing a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS. The method also includes determining a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data, and separating the plurality of NVRAMS into groups based on the trend in the failure metric as a function of testing cycles. A corresponding computer program product and computer system are also disclosed herein.

Claims

1. A method, executed by one or more processors, for sorting flash memories, the method comprising:

testing, via the one or more processors, a failure metric for each of a plurality of flash memories over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of flash memories;

weighting, via the one or more processors, the failure metric data according to the testing session;

determining, via the one or more processors, a trend in the failure metric as a function of testing cycles for each of the plurality of flash memories from the failure metric data;

repetitively conducting testing sessions, via the one or more processors, until a selected confidence level is attained for the trend in the failure metric as a function of testing cycles;

clustering, via the one or more processors, the trends in the failure metric as a function of testing cycles to provide a plurality of clustered groups for the failure metric data;

physically separating the plurality of flash memories into routing groups and routing the routing groups via equipment controlled by the one or more processors, according to the plurality of clustered groups;

wherein the failure metric comprises grown bad blocks; and

wherein the plurality of clustered groups comprise a scrap or rework group, an acceptable quality group, and an exceptional quality group and routing the routing groups comprises routing the scrap or rework group to scrapping or reworking stations within a manufacturing environment.