Passivation structure of fin field effect transistor

• US 9,530,710 B2
• Filed: 07/31/2015
• Issued: 12/27/2016
• Est. Priority Date: 10/07/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Yen-Yu, Shih, Chi-Yuan, Yeh, Ling-Yen, Wann, Clement Hsingjen
• Primary Examiner(s): Tran, Thanh Y
• Application Number:
  US14/815,027
• Publication Number:
  US 20150340302A1
• Time in Patent Office: 515 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02318 post-treatment
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower fin portion comprising a first semiconductor material having a first lattice constant; an upper fin portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant; a middle fin portion comprising a third semiconductor material having a third lattice constant between the first lattice constant and the second lattice constant; and a passivation structure surrounding the fin structure comprising a lower passivation portion surrounding the lower fin portion comprising a first oxynitride of the first semiconductor material; an upper passivation portion surrounding the upper fin portion comprising a second oxynitride of the second semiconductor material; and a middle passivation portion surrounding the middle fin portion comprising a third oxynitride of the third semiconductor material.

Claims

1. A method of fabricating a fin field effect transistor, the method comprising:

forming a first fin on a semiconductor substrate, the first fin comprising a first semiconductor material, a second semiconductor material over the first semiconductor material, and a third semiconductor material over the second semiconductor material, the first semiconductor material having a first lattice constant, the second semiconductor material having a second lattice constant, the third semiconductor material having a third lattice constant, the first lattice constant being different than the second lattice constant, the second lattice constant being different than the third lattice constant;

performing an oxidation process along sidewalls of the first fin; and

performing a nitridation process along sidewalls of the first fin, the nitridation process forming a nitride layer along sidewalls of the first fin, the nitride layer having a first portion comprising elements of the first semiconductor material, a second portion comprising elements of the second semiconductor material, and a third portion comprising elements of the third semiconductor material.

2. The method of claim 1, wherein the performing the oxidation process comprises a rapid thermal oxidation process.

3. The method of claim 2, wherein the performing the nitridation process comprises a decoupled plasma nitridation process.

4. The method of claim 2, wherein the performing the nitridation process comprises a rapid thermal nitridation process.

5. The method of claim 4, wherein the rapid thermal nitridation process is performed at a temperature of about 400°

C. to about 800°

C.

6. The method of claim 1, further comprising performing a post-nitridation anneal process.

7. A method of fabricating a fin field effect transistor, the method comprising:

forming a first semiconductor layer over a semiconductor substrate, the first semiconductor layer having a different lattice constant than the semiconductor substrate;

forming a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a different lattice constant than the first semiconductor layer;

forming a plurality of trenches that extends through the first semiconductor layer, the second semiconductor layer, and into the semiconductor substrate to form a fin structure between adjacent trenches;

forming a passivation layer along sidewalls and a bottom of the trenches, the passivation layer comprising a nitride layer; and

forming an isolation layer over the nitride layer along opposing sides of the fin structure.

8. The method of claim 7, wherein the forming the first semiconductor layer comprises epitaxially growing the first semiconductor layer on the semiconductor substrate, and wherein the forming the second semiconductor layer comprises epitaxially growing the second semiconductor layer on the first semiconductor layer.

9. The method of claim 7, wherein a lattice constant of the first semiconductor layer is greater than a lattice constant of the semiconductor substrate.

10. The method of claim 9, wherein a lattice constant of the second semiconductor layer is greater than the lattice constant of the first semiconductor layer.

11. The method of claim 7, wherein the nitride layer is an oxynitride layer.

12. The method of claim 7, wherein the forming the passivation layer comprises:

performing an oxidation process on the fin structure; and

performing a nitridation process on the fin structure.

13. The method of claim 12, wherein the oxidation process is performed prior to performing the nitridation process.

14. The method of claim 7, wherein the passivation layer extends over a top of the fin structure.

15. A fin field effect transistor (FinFET) comprising:

a fin extending from a substrate, the fin having a first semiconductor material, a second semiconductor material over the first semiconductor material, and a third semiconductor material over the second semiconductor material, the first semiconductor material having a first lattice constant, the second semiconductor material having a second lattice constant, the third semiconductor material having a third lattice constant, the first lattice constant being different than the second lattice constant, the second lattice constant being different than the third lattice constant; and

a passivation layer over the fin, the passivation layer comprising a first nitride along sidewalls of the first semiconductor material, a second nitride along sidewalls of the second semiconductor material, and a third nitride along sidewalls of the third semiconductor material.

16. The FinFET of claim 15, wherein the first nitride comprises a first oxynitride, the second nitride comprises a second oxynitride, and the third nitride comprises a third oxynitride.

17. The FinFET of claim 16, wherein the passivation layer comprises a fourth oxynitride extending over an upper surface of the fin, a first N/O ratio of the fourth oxynitride is equal to or greater than a second N/O ratio of the third oxynitride.

18. The FinFET of claim 17, wherein a ratio of the first N/O ratio to the second N/O ratio is from about 1 to about 1.3.

19. The FinFET of claim 15, further comprising an isolation layer over the passivation layer, the isolation layer extending above an interface between the second semiconductor material and the third semiconductor material.

20. The FinFET of claim 19, a gate dielectric over the passivation layer and the isolation layer.