Metallic etch stop layer in a three-dimensional memory structure

• US 9,530,788 B2
• Filed: 03/17/2015
• Issued: 12/27/2016
• Est. Priority Date: 03/17/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Oginoe, Tomohiro, Honma, Ryoichi, Terahara, Masanori
• Primary Examiner(s): STARK, JARRETT J
• Application Number:
  US14/659,963
• Publication Number:
  US 20160276359A1
• Time in Patent Office: 651 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A dielectric liner, a bottom conductive layer, and a stack of alternating layers including insulator layers and spacer material layers are sequentially formed over a substrate. A memory opening extending through the stack can be formed by an anisotropic etch process that employs the bottom conductive layer as an etch stop layer. The memory opening is extended downward by etching through the bottom conductive layer and the dielectric liner, while minimizing an overetch into the substrate. A memory stack structure can be formed in the memory opening. Subsequently, a backside contact trench can be formed through the stack employing the bottom conductive layer as an etch stop layer. The spacer material layers can be removed to form backside recesses, which are filled with a conductive material to form electrically conductive layers. The remaining portion of the bottom conductive layer can be employed as a source select gate electrode.

Claims

1. A monolithic three-dimensional memory device, comprising:

a dielectric liner contacting a top surface of a semiconductor substrate;

a bottom conductive layer contacting a top surface of the dielectric liner;

a stack of alternating layers comprising insulator layers and electrically conductive layers and located over the bottom conductive layer;

a memory opening extending through the stack, the bottom conductive layer, and the dielectric liner; and

a memory film located within the memory opening, wherein a bottommost surface of the memory film is coplanar with a bottom surface of the dielectric liner,

wherein the bottom conductive layer comprises;

a bottom metallic liner comprising a first conductive metallic compound and contacting a top surface of the dielectric liner, and

a bottom metallic material layer comprising a first metallic material selected from an elemental metal and an alloy of at least two elemental metals and contacting the bottom metallic liner; and

wherein a horizontal interface between the bottom metallic liner and the bottom metallic material layer is adjoined to an outer sidewall of the memory film.

2. The monolithic three-dimensional memory device of claim 1, wherein a top surface of the bottom metallic material layer contacts a bottom surface of a bottommost layer among the insulator layers of the stack.

3. The monolithic three-dimensional memory device of claim 1, wherein the bottom metallic material layer is in physical contact with a sidewall of the memory film.

4. The monolithic three-dimensional memory device of claim 1, wherein each of the electrically conductive layers comprise:

a metallic liner comprising a second conductive metallic compound and contacting at least one horizontal surface of the insulator layers; and

a metallic fill material layer comprising a second metallic material selected from an elemental metal and an alloy of at least two elemental metals, contacting the metallic liner, and spaced from the insulator layers at least by the metallic liner.

5. The monolithic three-dimensional memory device of claim 4, wherein the metallic fill material layer does not contact the memory film, and is laterally spaced from the memory film by the metallic liner.

6. The monolithic three-dimensional memory device of claim 4, wherein the bottom metallic liner and the metallic liners differ in at least one of thickness and composition.

7. The monolithic three-dimensional memory device of claim 4, wherein the bottom metallic material layer and the metallic fill material layers differ in composition.

8. The monolithic three-dimensional memory device of claim 4, wherein:

the first conductive metallic compound comprises a first metallic nitride; and

the second conductive metallic compound comprises a second metallic nitride.

9. The monolithic three-dimensional memory device of claim 1, wherein an interface between the bottommost surface of the memory film and the semiconductor substrate is coplanar with an interface between the bottom surface of the dielectric liner and the semiconductor substrate.

10. The monolithic three-dimensional memory device of claim 1, further comprising a semiconductor channel laterally surrounded by the memory film and extending into the semiconductor substrate.

11. The monolithic three-dimensional memory device of claim 1, further comprising a backside contact via structure extending through the stack, the bottom conductive layer, and the dielectric liner, wherein the bottom conductive layer laterally surrounds the backside contact via structure.

12. The monolithic three-dimensional memory device of claim 11, further comprising an insulating spacer contacting a sidewall of the backside contact via structure, a sidewall of the bottom conductive layer, and a top surface of the semiconductor substrate.

13. The monolithic three-dimensional memory device of claim 1, wherein:

the dielectric liner comprises a silicon oxide layer; and

the bottom conductive layer comprises a tungsten layer.

14. The monolithic three-dimensional memory device of claim 1, wherein:

each of the electrically conductive layers has a seam which extends horizontally and at which two portions of a respective electrically conductive layer are adjoined; and

the bottom metallic material layer is free of any seam therein.

15. The monolithic three-dimensional memory device of claim 1, wherein:

the monolithic three-dimensional memory device is a vertical NAND memory device; and

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND memory device.

16. The monolithic three-dimensional memory device of claim 15, wherein:

the bottom conductive layer is a source select gate electrode of a source select transistor of the vertical NAND memory device;

the dielectric liner comprises a gate dielectric of the source select transistor; and

a portion of the semiconductor substrate located below the dielectric liner comprises at least a portion of the channel of the source select transistor.

17. The monolithic three-dimensional memory device of claim 15, wherein:

the semiconductor substrate comprises a silicon substrate;

the vertical NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in the first device level of the three-dimensional array of NAND strings is located over another memory cell in the second device level of the three-dimensional array of NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and

the three-dimensional array of NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the silicon substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

18. The monolithic three-dimensional memory device of claim 1, wherein both the bottom metallic material layer and the bottom metallic liner physically contact a portion of the outer sidewall of the memory film.

19. A monolithic three-dimensional memory device, comprising:

a dielectric liner contacting a top surface of a semiconductor substrate;

a bottom conductive layer contacting a top surface of the dielectric liner;

a stack of alternating layers comprising insulator layers and electrically conductive layers and located over the bottom conductive layer;

a memory opening extending through the stack, the bottom conductive layer, and the dielectric liner; and

a memory film located within the memory opening, wherein a bottommost surface of the memory film is coplanar with a bottom surface of the dielectric liner,

wherein the bottom conductive layer comprises;

a bottom metallic liner comprising a first conductive metallic compound and contacting a top surface of the dielectric liner, and

a bottom metallic material layer comprising a first metallic material selected from an elemental metal and an alloy of at least two elemental metals and contacting the bottom metallic liner; and

wherein both the bottom metallic material layer and the bottom metallic liner physically contact a portion of an outer sidewall of the memory film.

20. The monolithic three-dimensional memory device of claim 19, wherein a top surface of the bottom metallic material layer contacts a bottom surface of a bottommost layer among the insulator layers of the stack.

21. The monolithic three-dimensional memory device of claim 19, wherein the bottom metallic material layer is in physical contact with a sidewall of the memory film.

22. The monolithic three-dimensional memory device of claim 19, wherein each of the electrically conductive layers comprise:

a metallic liner comprising a second conductive metallic compound and contacting at least one horizontal surface of the insulator layers; and

a metallic fill material layer comprising a second metallic material selected from an elemental metal and an alloy of at least two elemental metals, contacting the metallic liner, and spaced from the insulator layers at least by the metallic liner.

23. The monolithic three-dimensional memory device of claim 22, wherein the metallic fill material layer does not contact the memory film, and is laterally spaced from the memory film by the metallic liner.

24. The monolithic three-dimensional memory device of claim 22, wherein the bottom metallic liner and the metallic liners differ in at least one of thickness and composition.

25. The monolithic three-dimensional memory device of claim 22, wherein the bottom metallic material layer and the metallic fill material layers differ in composition.

26. The monolithic three-dimensional memory device of claim 22, wherein:

the first conductive metallic compound comprises a first metallic nitride; and

the second conductive metallic compound comprises a second metallic nitride.

27. The monolithic three-dimensional memory device of claim 19, wherein an interface between the bottommost surface of the memory film and the semiconductor substrate is coplanar with an interface between the bottom surface of the dielectric liner and the semiconductor substrate.

28. The monolithic three-dimensional memory device of claim 19, further comprising a semiconductor channel laterally surrounded by the memory film and extending into the semiconductor substrate.

29. The monolithic three-dimensional memory device of claim 19, further comprising:

a backside contact via structure extending through the stack, the bottom conductive layer, and the dielectric liner, wherein the bottom conductive layer laterally surrounds the backside contact via structure; and

an insulating spacer contacting a sidewall of the backside contact via structure, a sidewall of the bottom conductive layer, and a top surface of the semiconductor substrate.

30. The monolithic three-dimensional memory device of claim 19, wherein:

the dielectric liner comprises a silicon oxide layer;

the bottom conductive layer comprises a tungsten layer;

each of the electrically conductive layers has a seam which extends horizontally and at which two portions of a respective electrically conductive layer are adjoined; and

the bottom metallic material layer is free of any seam therein.

31. The monolithic three-dimensional memory device of claim 19, wherein:

the monolithic three-dimensional memory device is a vertical NAND memory device; and

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND memory device.

32. The monolithic three-dimensional memory device of claim 31, wherein:

the bottom conductive layer is a source select gate electrode of a source select transistor of the vertical NAND memory device;

the dielectric liner comprises a gate dielectric of the source select transistor;

a portion of the semiconductor substrate located below the dielectric liner comprises at least a portion of the channel of the source select transistor;

the semiconductor substrate comprises a silicon substrate;

the vertical NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in the first device level of the three-dimensional array of NAND strings is located over another memory cell in the second device level of the three-dimensional array of NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and

the three-dimensional array of NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the silicon substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.