Layered structure, thin film transistor array, and method of manufacturing the same

• US 9,530,809 B2
• Filed: 03/20/2015
• Issued: 12/27/2016
• Est. Priority Date: 09/26/2012
• Status: Active Grant

• Current Assignee: Toppan Printing Co., Ltd. (TOPPAN Holdings, Inc.)
• Original Assignee: Toppan Printing Co., Ltd. (TOPPAN Holdings, Inc.)
• Inventors: Ishizaki, Mamoru, Hatta, Kaoru
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): DINKE, BITEW A
• Application Number:
  US14/664,683
• Publication Number:
  US 20150221685A1
• Time in Patent Office: 648 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence

Abstract

A layered structure includes a first electrode layer on an insulating substrate, a first insulating film on the first electrode layer, a second electrode layer on the first insulating film, a second insulating film on the second electrode layer, and a third electrode layer on the second insulating film. The first electrode layer, an opening of the first insulating film, the second electrode layer, an opening of the second insulating film, and the third electrode layer have a stack structure that causes the first electrode layer and the second electrode layer to be connected. The third electrode layer relays or reinforces, through the opening of the second insulating film, a connection between the first electrode layer and the second electrode layer formed on the first insulating film.

Claims

1. A layered structure comprising:

a first electrode layer on an insulating substrate, the first electrode layer including a gate wire;

a gate electrode connected to the gate wire;

a capacitor wire; and

a capacitor electrode connected to the capacitor wire;

a first insulating film on the first electrode layer;

a second electrode layer on the first insulating film, the second electrode layer including a source wire;

a source electrode connected to the source wire;

a drain electrode; and

a pixel electrode connected to the drain electrode;

a semiconductor located between the source electrode and the drain electrode, the gate electrode overlapping the semiconductor via the first insulating film, the capacitor electrode overlapping the pixel electrode via the first insulating film;

a second insulating film on the second electrode layer and having an opening on the pixel electrode;

a third electrode layer on the second insulating film, the third electrode layer comprising a plurality of reinforcement electrodes and including an upper pixel electrode connected to the pixel electrode via the opening, and

a floating-gate thin film transistor,

wherein the first electrode layer, an opening of the first insulating film, the second electrode layer, an opening of the second insulating film, and the third electrode layer have a stack structure that causes the first electrode layer and the second electrode layer to be connected,

the third electrode layer relaying or reinforcing, through the opening of the second insulating film, a connection between the first electrode layer and the second electrode layer,

a common electrode around the thin film transistor array, the common electrode comprising a gate common electrode and a source common electrode;

gate protective elements located between the gate wires and the gate common electrode;

source protective elements located between the source wires and the source common electrode, the common electrode being directly connected to a ground potential or the ground potential via a resistor,

wherein;

the gate common electrode is included in the second electrode layer,

the source common electrode is included in the first electrode layer,

at least one of the gate protective elements and the source protective elements comprises;

a pair of diode-connected thin film transistors connected in parallel to each other such that one of the diode-connected thin film transistors is opposite in direction to the other thereof;

a pair of diode-connected thin film transistors connected in series to each other such that one of the diode-connected thin film transistors is opposite in direction to the other thereof;

or

a floating-gate thin film transistor, and

the third electrode layer relays or reinforces, as the connection between the first electrode layer and the second electrode layer, at least one of;

a short-circuit portion between a gate electrode and a source electrode of the gate protective element;

a short-circuit portion between a gate electrode and a source electrode of the source protective element;

a connection portion between the gate wire and the gate protective element; and

a connection portion between the source protective element and the source common electrode.

2. A thin film transistor array comprising, on an insulating substrate:

a first electrode layer including;

a gate wire;

a gate electrode connected to the gate wire;

a capacitor wire; and

a capacitor electrode connected to the capacitor wire;

a gate insulating film on the first electrode layer;

a second electrode layer on the gate insulating film, the second electrode layer including;

a source wire;

a source electrode connected to the source wire;

a drain electrode; and

a pixel electrode connected to the drain electrode;

a semiconductor located between the source electrode and the drain electrode, the gate electrode overlapping the semiconductor via the gate insulating film, the capacitor electrode overlapping the pixel electrode via the gate insulating film;

an interlayer insulating film having an opening on the pixel electrode;

a third electrode layer including an upper pixel electrode connected to the pixel electrode via the opening,

a common electrode around the thin film transistor array, the common electrode comprising a gate common electrode and a source common electrode;

gate protective elements located between the gate wires and the gate common electrode; and

source protective elements located between the source wires and the source common electrode, the common electrode being directly connected to a ground potential or the ground potential via a resistor,

wherein the first electrode layer, an opening of the gate insulating film, the second electrode layer, the opening of the interlayer insulating film, and the third electrode layer have a stack structure that causes the first electrode layer and the second electrode layer to be connected,

wherein the third electrode layer relays or reinforces, through the opening of the interlayer insulating film, a connection between the first electrode layer and the second electrode layer formed on the gate insulating film, and

wherein the third electrode layer comprises a plurality of reinforcement electrodes,

wherein

the gate common electrode is included in the second electrode layer,

the source common electrode is included in the first electrode layer,

at least one of the gate protective elements and the source protective elements comprises;

a pair of diode-connected thin film transistors connected in parallel to each other such that one of the diode-connected thin film transistors is opposite in direction to the other thereof;

a pair of diode-connected thin film transistors connected in series to each other such that one of the diode-connected thin film transistors is opposite in direction to the other thereof;

or

a floating-gate thin film transistor, and

the third electrode layer relays or reinforces, as the connection between the first electrode layer and the second electrode layer, at least one of;

a short-circuit portion between a gate electrode and a source electrode of the gate protective element;

a short-circuit portion between a gate electrode and a source electrode of the source protective element;

a connection portion between the gate wire and the gate protective element; and

a connection portion between the source protective element and the source common electrode.

3. The thin film transistor array according to claim 2, wherein:

a gate connection electrode and a source connection electrode of the thin film transistor array are included in the first electrode layer, and

the third electrode layer relays or reinforces, as the connection between the first electrode layer and the second electrode layer, a connection portion between the source connection electrode and the source wire.

4. The thin film transistor array according to claim 2, wherein:

a gate connection electrode and a source connection electrode of the thin film transistor array are included in the second electrode layer, and

the third electrode layer relays or reinforces, as the connection between the first electrode layer and the second electrode layer, a connection portion between the gate wire and the gate connection electrode.

5. A thin film transistor array comprising, on an insulating substrate:

a first electrode layer including;

a source wire;

a source electrode connected to the source wire;

a drain electrode; and

a pixel electrode connected to the drain electrode;

semiconductors between the source electrodes and the drain electrodes;

a gate insulating film having an opening on the pixel electrode;

a second electrode layer on the gate insulating film, the second electrode layer including;

a gate wire;

a gate electrode connected to the gate wire;

a capacitor wire; and

a capacitor electrode connected to the capacitor wire,

the gate electrode overlapping the semiconductor via the gate insulating film, the capacitor electrode overlapping the pixel electrode via the gate insulating film;

an interlayer insulating film having an opening above the opening of the gate insulating film; and

a third electrode layer including an upper pixel electrode connected to the pixel electrode via the opening of the interlayer insulating film,

a common electrode around the thin film transistor array, the common electrode comprising a gate common electrode and a source common electrode;

a gate protective element located between the gate wire and the gate common electrode;

a source protective element located between the source wire and the source common electrode, the common electrode being directly connected to a ground potential or the ground potential via a resistor,

wherein the first electrode layer, the opening of the gate insulating film, the second electrode layer, the opening of the interlayer insulating film, and the third electrode layer have a stack structure that causes the first electrode layer and the second electrode layer to be connected,

wherein the third electrode layer relays or reinforces, through the opening of the interlayer insulating film, a connection between the first electrode layer and the second electrode layer formed on the gate insulating film, and

wherein the third electrode layer comprises a plurality of reinforcement electrodes,

wherein;

the gate common electrode is included in the first electrode layer,

the source common electrode is included in the second electrode layer,

at least one of the gate protective element and the source protective element comprises;

a pair of diode-connected thin film transistors connected in parallel to each other such that one of the diode-connected thin film transistors is opposite in direction to the other thereof;

a pair of diode-connected thin film transistors connected in series to each other such that one of the diode-connected thin film transistors is opposite in direction to the other thereof;

or

a floating-gate thin film transistor, and

the third electrode layer relays or reinforces, as the connection between the first electrode layer and the second electrode layer, at least one of;

a short-circuit portion between a drain electrode and a gate electrode of the gate protective element;

a short-circuit portion between a drain electrode and a gate electrode of the source protective element;

a connection portion between the gate protective element and the gate wire; and

a connection portion between the source common electrode and the source protective element.

6. The thin film transistor array according to claim 5, wherein:

a gate connection electrode and a source connection electrode of the thin film transistor array are included in the first electrode layer, and

the third electrode layer relays or reinforces, as the connection between the first electrode layer and the second electrode layer, a connection portion between the gate connection electrode and the gate wire.

7. The thin film transistor array according to claim 5, wherein:

a gate connection electrode and a source connection electrode of the thin film transistor array are included in the second electrode layer, and

the third electrode layer relays or reinforces, as the connection between the first electrode layer and the second electrode layer, a connection portion between the source wire and the source connection electrode.