Transistor structures having reduced electrical field at the gate oxide and methods for making same

• US 9,530,844 B2
• Filed: 12/28/2012
• Issued: 12/27/2016
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Zhang, Qingchun, Hull, Brett
• Primary Examiner(s): Huynh, Andy
• Assistant Examiner(s): Yechuri, Sitaramarao S
• Application Number:
  US13/730,133
• Publication Number:
  US 20140183553A1
• Time in Patent Office: 1,460 Days
• Field of Search: 257/77
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0688 characterised by the particular shape of a junction between semiconductor regions
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66378 the other device being a controlling field-effect device
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A transistor device having reduced electrical field at the gate oxide interface is disclosed. In one embodiment, the transistor device comprises a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide. The transistor device has a P+ region within a JFET region of the transistor device in order to reduce an electrical field on the gate oxide.

Claims

1. A transistor device having a gate that is at least partially in contact with a gate oxide, a source, and a drain, the transistor device comprising:

a well region of a first conductivity type;

a region of a second conductivity type on the well region;

a buried channel layer adjacent a first surface of the transistor device, the buried channel layer extending across a portion of the region of the second conductivity type and being at least partially covered by the gate oxide where the transistor device has a reduced electrical field on the gate oxide;

a junction field effect (JFET) region adjacent the well region;

a drift layer below the well region;

a region of the first conductivity type at the JFET region and adjacent the well region and the region of the second conductivity type, wherein the JFET region extends between the region of the first conductivity type and the buried channel layer; and

first and second regions of the first conductivity type introduced at the JFET region, wherein the well region is implanted to a first depth within the transistor device and at least one of the first and second regions is implanted at a second depth within the JFET region that is between half the first depth and the first depth of the well region.

2. A transistor device according to claim 1, wherein the first and second regions of the first conductivity type introduced at the JFET region reduces an electrical field at the gate oxide.

3. A transistor device according to claim 1, wherein the transistor device is an MOSFET.

4. A transistor device according to claim 1, wherein the transistor device is an insulated gate bipolar transistor.

5. A transistor device according to claim 1, wherein the first conductivity type is P+, and the second conductivity type is N+.

6. A transistor device according to claim 1, wherein a body of the transistor device comprises silicon carbide.

7. A transistor device according to claim 1, wherein one of the first and second regions of the first conductivity type introduced at the JFET region is a P+ region and is introduced substantially in the middle of the JFET region.

8. A transistor device according to claim 1, wherein one of the first and second regions of the first conductivity type introduced at the JFET region is a P+ region and is connected to the source, which effectively shields the electrical field from a side of the transistor device having the drain.

9. A transistor device according to claim 1, wherein one of the first and second regions of the first conductivity type introduced within the JFET region is a P+ region and is shallower in depth than the well region.

10. A transistor device according to claim 1, wherein one of the first and second regions of the first conductivity type introduced within the JFET region is a P+ region and is between about approximately 0.1 microns and about approximately 0.3 microns in depth.

11. A transistor device according to claim 1, wherein one of the first and second regions of the first conductivity type introduced within the JFET region is a P+ region and is between about approximately 0.5 microns and about approximately 1.0 microns in width.

12. A transistor device according to claim 1, wherein a width of the JFET region is between about approximately 2.0 and about approximately 3.6 microns.

13. A transistor device according to claim 1, wherein the at least one of the first and second regions has a top portion that does not extend to the buried channel.

14. A MOSFET having a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide, the MOSFET comprising:

a P+-type well implanted to a first depth within the MOSFET;

an N+-type region on the P+-type well;

a buried channel layer adjacent a first surface of the MOSFET, the buried channel layer extending across a portion of the N+-type region;

a junction field effect (JFET) region adjacent the P+ type well;

a first P+ region at the JFET region and adjacent the well region and the N+ type region, wherein the JFET region extends between the first P+ region and the buried channel layer;

a second P+ region at the JFET region in order to reduce an electrical field on the gate oxide, wherein the second P+ region is at a second depth between half the first depth and the first depth of the P+-type well.

15. A MOSFET according to claim 14, wherein a body of the MOSFET comprises silicon carbide.

16. A MOSFET according to claim 14, wherein the second P+ region is substantially in the middle of the JFET region.

17. A MOSFET according to claim 14, wherein the second P+ region is connected to the source, which effectively shields the electrical field from a side of the MOSFET having the drain.

18. A MOSFET according to claim 14, wherein the second P+ region is between about approximately 0.1 and about approximately 0.3 microns in depth.

19. A MOSFET according to claim 14, wherein the second P+ region is between about approximately 0.5 microns and about approximately 1.0 microns in width.

20. A MOSFET according to claim 14, wherein a width of the JFET region is between about approximately 2.0 and about approximately 3.6 microns.

21. A MOSFET according to the claim 14, further comprising a third P+ region.

22. A MOSFET according to claim 21, wherein one of the second P+ region and the third P+ region is shallower in depth than the P+ well.

23. A MOSFET according to the claim 14, wherein the second P+ region has a top portion that does not extend to the buried channel layer.